RTL8309SB REALTEK, RTL8309SB Datasheet
RTL8309SB
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RTL8309SB Summary of contents
Page 1
... RTL8309SB SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER DATASHEET Rev. 1.4 09 July 2004 Track ID: JATR-1076-21 ...
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... This document provides detailed user guidelines to achieve the best performance when implementing a 2-layer board PC design with the RTL8309SB Single-Chip 9-port 10/100Mbps Switch Controller. Though every effort has been made to assure that this document is current and accurate, more information may have become available subsequent to the production of this guide ...
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... Add explanation of Indirect Access Data in PHY 7 Register 17~20. Removed PHY0~PHY7 REG2 and REG3 info. Update pin number ordering on Pin Description Table. Change the term “Auto MDIX” to “Crossover Detection and auto correction”. Removed QoS feature for IPv6. iii RTL8309SB Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Port 0 Control 2..................................................................................................................................................21 6.2.4. Port 0 Control 3..................................................................................................................................................21 6.2.5. Port 0 Control 4..................................................................................................................................................21 6.2.6. IP Address...........................................................................................................................................................22 6.2.7. Port 1 Control 0..................................................................................................................................................23 6.2.8. Port 1 Control 1..................................................................................................................................................23 Single-Chip 9-Port 10/100Mbps Switch Controller Table of Contents ..........................................................................................................................................7 INS P ...............................................................................................................................7 INS ................................................................................................................................................9 SMI P .............................................................................................................................11 INS ..................................................................................................................................17 ..........................................................................................................................................20 iv RTL8309SB Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Port 5 Control 0..................................................................................................................................................34 6.4.2. Port 5 Control 1..................................................................................................................................................34 6.4.3. Port 5 Control 2..................................................................................................................................................35 6.4.4. Port 5 Control 3..................................................................................................................................................35 6.4.5. Port 5 Control 4..................................................................................................................................................35 6.4.6. Port 6 Control 0..................................................................................................................................................36 6.4.7. Port 6 Control 1..................................................................................................................................................36 6.4.8. Port 6 Control 2..................................................................................................................................................36 Single-Chip 9-Port 10/100Mbps Switch Controller ..........................................................................................................................................32 ..........................................................................................................................................34 v RTL8309SB Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... PHY 1 Register 18~19: IP Priority Address [B].................................................................................................49 7.2.8. PHY 1 Register 22: Port 1 Control 0..................................................................................................................50 7.2.9. PHY 1 Register 23: Port 1 Control 1..................................................................................................................50 7.2.10. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]...................................................................................50 7.2.11. PHY 1 Register 25: VLAN Entry [B] ..................................................................................................................50 Single-Chip 9-Port 10/100Mbps Switch Controller vi Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
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... PHY 4 Register 16~18: ISP MAC Address .........................................................................................................54 7.5.7. PHY 4 Register 22: Port 4 Control 0..................................................................................................................54 7.5.8. PHY 4 Register 23: Port 4 Control 1..................................................................................................................54 7.5.9. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]...................................................................................55 7.5.10. PHY 4 Register 25: VLAN Entry [E] ..................................................................................................................55 Single-Chip 9-Port 10/100Mbps Switch Controller vii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
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... PHY 7 Register 6: Auto-Negotiation Expansion.................................................................................................61 7.8.6. PHY 7 Register 16: indirect Access Control.......................................................................................................61 7.8.7. PHY 7 Register 17~20: Indirect Access Data.....................................................................................................62 7.8.8. PHY 7 Register 22: Port 7 Control 0..................................................................................................................62 7.8.9. PHY 7 Register 23: Port 7 Control 1..................................................................................................................62 Single-Chip 9-Port 10/100Mbps Switch Controller viii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
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... QoS Operation....................................................................................................................................................77 8.3.4. Insert/Remove VLAN Priority Tag......................................................................................................................78 8.3.5. Port VID (PVID) ................................................................................................................................................79 8.3.6. Port Trunking .....................................................................................................................................................79 8.3.7. ISP MAC Address Translation ............................................................................................................................79 8.3.8. Lookup Table Access...........................................................................................................................................81 Single-Chip 9-Port 10/100Mbps Switch Controller F O .......................................................................................66 UNCTIONAL VERVIEW O ....................................................................................................................68 VERVIEW O ...................................................................................................................74 VERVIEW ix RTL8309SB Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... PERATING ANGE 9. HARACTERISTICS 9. HARACTERISTICS 9. IGITAL IMING HARACTERISTICS 9. HERMAL HARACTERISTICS 10. SYSTEM APPLICATIONS ...........................................................................................................................................95 11. DESIGN AND LAYOUT GUIDE..................................................................................................................................96 12. MECHANICAL DIMENSIONS ...................................................................................................................................99 12.1. N 128-P LQFP D OTES FOR IN Single-Chip 9-Port 10/100Mbps Switch Controller R ................................................................................................................................90 ATINGS .............................................................................................................................................90 .............................................................................................................................................91 .........................................................................................................................92 ...................................................................................................................................94 ................................................................................................................100 IMENSIONS x RTL8309SB Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Table 26. Port 1 Control 3............................................................................................................................24 Table 27. Port 1 Control 4............................................................................................................................24 Table 28. IP Mask ........................................................................................................................................25 Table 29. Port 2 Control 0............................................................................................................................25 Table 30. Port 2 Control 1............................................................................................................................26 Table 31. Port 2 Control 2............................................................................................................................26 Table 32. Port 2 Control 3............................................................................................................................26 Table 33. Port 2 Control 4............................................................................................................................27 Single-Chip 9-Port 10/100Mbps Switch Controller List of Tables xi RTL8309SB Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... Table 62. Port 7 Control 2............................................................................................................................38 Table 63. Port 7 Control 3............................................................................................................................39 Table 64. Port 7 Control 4............................................................................................................................39 Table 65. PHY 0 Register 0: Control ...........................................................................................................40 Table 66. PHY 0 Register 1: Status .............................................................................................................41 Table 67. PHY 0 Register 4: Auto-Negotiation Advertisement...................................................................42 Table 68. PHY 0 Register 5: Auto-Negotiation Link Partner Ability ..........................................................42 Single-Chip 9-Port 10/100Mbps Switch Controller xii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
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... Table 100. PHY 7 Register 16: Indirect Access Control .............................................................................61 Table 101. PHY 7 Register 17~20: Indirect Access Data ............................................................................62 Table 102. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H].........................................................62 Table 103. PHY 7 Register 25: VLAN Entry [H]........................................................................................63 Single-Chip 9-Port 10/100Mbps Switch Controller xiii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
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... Table 114. Absolute Maximum Ratings.......................................................................................................90 Table 115. Operating Range ........................................................................................................................90 Table 116. DC Characteristics .....................................................................................................................90 Table 117. AC Characteristics......................................................................................................................91 Table 118. Digital Timing Characteristics ...................................................................................................93 Table 119. Thermal Operating Range ..........................................................................................................94 Table 120. Thermal Resistance....................................................................................................................95 Single-Chip 9-Port 10/100Mbps Switch Controller xiv Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
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... Figure 20. Reception Data Timing of MII/SNI/SMI Interface ....................................................................92 Figure 21. Transmission Data Timing of MII/SNI/SMI Interface...............................................................92 Figure 22. Cross-section of 128-Pin PQFP..................................................................................................94 Figure 23. Application for Transformer with Connected Central Tap .........................................................97 Figure 24. Bob Smith Termination ..............................................................................................................98 Single-Chip 9-Port 10/100Mbps Switch Controller List of Figures xv RTL8309SB Datasheet Track ID: JATR-1076-21 Rev. 1.4 ...
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... The RTL8309SB is capable of preventing broadcast storms by setting strapping pins upon system reset. When this function is enabled, it will drop broadcast packets after receiving 64 continuous broadcast packets. This counter will be reset to 0 every 800ms or when the RTL8309SB receives a non-broadcast packet. The RTL8309SB displays the port status via four LED indicators (with optional blinking time setting). ...
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... In router applications, the router may want to know which input port this packet came from. The RTL8309SB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. In this function, the VID information carried in the VLAN tag will be changed to PVID. The RTL8309SB also provides an option to admit VLAN tagged packet with a specific PVID only ...
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... Optional Leaky VLAN for unicast packet. Optional 802.1P/Q tag insertion or removal on per-port basis (egress). 25MHz crystal input. 0.18µm, CMOS technology. 128-pin PQFP package. 1.8V core voltage. Independent power options for 2.5V or 3.3V MII interface. 3 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
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... Flow Control 10/100 MAC 7 TX/RX FIFO Flow Control 10/100 MAC 8 TX/RX MAC FIFO Mode PHY Mode Mode Select Figure 1. Block Diagram 4 RTL8309SB Datasheet RTL8309SB Look-up Table (1024-entries) Queue Management Buffer Management Packet Buffer EEPROM Interface Control Registers Track ID: JATR-1076-21 Rev. 1.4 ...
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... Test Pin 121 IBREF 122 123 VDDA TXON[0] 124 125 TXOP[0] 126 VSSA 127 RXIP[0] 128 RXIN[0] Single-chip 9-port 10/100Mbps Switch Controller RTL8309SB Figure 2. Pin Assignments 5 RTL8309SB Datasheet 64 MCOL/PCOL 63 VSSIO 62 VDDIO 61 MTXD[3]/PRXD[3] 60 MTXD[2]/PRXD[2] 59 MTXD[1]/PRXD[1] 58 MTXD[0]/PRXD[0] 57 MTXEN/PRXDV 56 MTXC/PRXC ...
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... I/O X1, 55, I/O X2, 56, I/O VDDPLL, 57, O NC, 58, I/O IBREF, 59, I/O VDDA, 60, I/O TXON[0], 61, I/O TXOP[0], 62, DVDD VSSA, 63, DGND RXIP[0], 64 I/O RXIN[0], 6 RTL8309SB Datasheet Pin No Type 65, I/O 66, I 67, I 68, I 69, I 70, I 71, DVDD 72, DGND 73, I/O 74, I/O 75, I/O 76, I/O 77, I/O 78, I/O 79 DVDD ...
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... For MII MAC mode, this pin represents MRXDV, MII receive data valid. For MII PHY mode, this pin represents PTXEN, MII transmit enable. For SNI PHY mode, this pin represents PTXEN, transmit enable. 7 RTL8309SB Datasheet Default Default Track ID: JATR-1076-21 Rev. 1.4 ...
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... Provides MII port (9 port) flow control status for MAC module at MII pu MAC/MII PHY/SNI PHY operation mode in real time. 1: MII port has flow control ability 0: MII port does not have flow control ability 8 RTL8309SB Datasheet th port) operating mode. Track ID: JATR-1076-21 Rev. 1.4 Default 11 ...
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... I Active low reset signal. To complete the reset function, this pin must be asserted for at least 10ms. After reset, about 30ms is needed for the RTL8309SB to complete the internal test function and initialization. Note: This pin is a Schmitt input pin. A Control transmit output waveform Vpp. ...
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... Collision, Duplex, Link+Act+Speed, Reserved LED_MODE[2:0]=011 -> Mode 3: Reserved, Duplex+Collision, Link+Act+Speed, 10/100 LED_MODE[2:0]=010 -> Mode 2: RxAct+10/100, TxAct+10/100, Link, Reserved LED_MODE[2:0]=001 -> Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, Reserved. LEDM_ODE[2:0]=000 -> Mode 0: Bi-color Speed, Duplex+Collision, Bi-color Link+Act, Reserved 10 RTL8309SB Datasheet nd LED. rd LED. th LED. Track ID: JATR-1076-21 Rev. 1.4 Default ...
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... EEPROM Serial Clock or MDC. This pin is three state when pin RESET#=0. When the RTL8309SB detects an EEPROM connected to it, this pin becomes SCL (output) to load the serial EEPROM upon reset. Then the pin changes to MDC (input) after reset. In this case, this pin should be pulled high (VDDIO 2 ...
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... I/O EEPROM Serial Data Input/Output or MDIO. This pin is three state when pin RESET#=0. When the RTL8309SB detects an EEPROM connected to it, this pin becomes SDA (input/output) to load the serial EEPROM upon reset. The pin changes to MDIO (input/output) after reset. When the RTL8309SB does not detect an EEPROM connected to it, this pin is MDIO (input/output) ...
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... Input upon reset = Enable aggressive back-off mechanism Enable more aggressive back-off mechanism in half duplex mode for performance enhancement. The back-off limitation will become 3 in this mode (default is 10) 0: Disable aggressive back-off mechanism in half duplex mode Output after reset = used for LED. 13 RTL8309SB Datasheet Default ...
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... Input upon reset = Weighted round robin ratio priority queue. pu The frame service ratio between the high priority queue and low priority queue is: 11=16:1 10=Always high priority queue first 01=8:1 00=4:1 Output after reset = used for LED. 14 RTL8309SB Datasheet Default Track ID: JATR-1076-21 Rev. 1.4 ...
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... Input upon reset = Select blinking speed of activity and collision I pu LED 43ms then Off 43ms 0: On 120ms then Off 120ms Note: This pin only affects LEDs that are configured in LED mode 1, 5, and 7. Output after reset = used for LED. 15 RTL8309SB Datasheet Default Track ID: JATR-1076-21 Rev. 1.4 ...
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... G Digital ground. P 2.5/3.3V digital VDD for MII interface. G Digital ground for MII interface. P 1.8V analog power for PLL. G 1.8V analog ground for PLL. P 1.8V analog power (Used for transmitters and equalizers). G Analog ground. 16 RTL8309SB Datasheet Default Track ID: JATR-1076-21 Rev. 1.4 ...
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... Disable aging function in the switch 1: An entry learned in the lookup table will be aged out not updated within an 800µs period 0: Disable fast aging function. The normal aging time of the RTL8309SB is around 200~300 seconds 1: Enable ISP MAC Address Translation 0: Disable ISP MAC Address Translation Table 10 ...
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... The switch will compare both the source and destination IP addresses of an incoming packet against the value, IP address [B] AND IP mask [B], to classify priority for the packet 0: The switch will not compare the source and destination IP addresses of an incoming packet against the value, IP address [B] AND IP mask [B] 18 RTL8309SB Datasheet Default 1 1 Default ...
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... Disable drop packet when SRAM full for 48 pass 1. This will result in SRAM run out 1: 90ppm TX IPG compensation 0: 65ppm TX IPG compensation 1: Disable loop detection function 0: Enable loop detection function 1: Lookup table is accessible via indirect access registers 0: Lookup table is not accessible 19 RTL8309SB Datasheet Default 0 1 111111 Default 0 1 ...
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... Disable 802.1p priority classification for ingress packets on port 0 0: Enable 802.1p priority classification on port 0 1: Disable Diffserv priority classification for ingress packets on port 0 0: Enable Diffserv priority classification on Port 0 1: Disable port priority function 0: Enable port priority function. Ingress packets from port 0 will be classified as high priority 20 RTL8309SB Datasheet Default ...
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... E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. VLAN Entry [A] This register along with byte 15.3~15.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A. This register along with byte 14.7~14.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A. 21 RTL8309SB Datasheet Default 1111 1000 Default 1111 1 ...
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... AND IP mask [B], to classify priority for the packet. IP Address [ priority for IP address [B] is enabled, the switch will compare the source IP address of an incoming packet against the value, IP address [B] AND IP mask [B], to classify priority for the packet. 22 RTL8309SB Datasheet Default 0xff 0xff 0xff ...
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... Enable Diffserv priority classification Disable port- 25.0 1: Disable port priority function based priority 0: Enable port priority function. Ingress packets from port 1 will be classified as high priority Single-chip 9-port 10/100Mbps Switch Controller Table 23. Port 1 Control 0 Table 24. Port 1 Control 1 23 RTL8309SB Datasheet Default Default 11 0 ...
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... This register along with byte 30.7~30.0 defines the IEEE 802.1Q 12-bit [11:8] 31.0 VLAN identifier of VLAN B. Single-chip 9-port 10/100Mbps Switch Controller Table 25. Port 1 Control 2 Table 26. Port 1 Control 3 VLAN Entry [B] Table 27. Port 1 Control 4 VLAN Entry [B] 24 RTL8309SB Datasheet Default 1111 1000 Default 1111 ...
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... Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Single-chip 9-port 10/100Mbps Switch Controller Table 28. IP Mask IP Mask [A] IP Mask [A] IP Mask [A] IP Mask [A] IP Mask [B] IP Mask [B] IP Mask [B] IP Mask [B] Table 29. Port 2 Control 0 25 RTL8309SB Datasheet Default 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff Default 11 11 Track ID: JATR-1076-21 Rev ...
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... Enable packet reception on port 2 0: Disable packet reception on port 2 Learning enable 43.1 1: Enable switch address learning capability 0: Disable switch address learning capability Reserved 43.0 Single-chip 9-port 10/100Mbps Switch Controller Table 30. Port 2 Control 1 Table 31. Port 2 Control 2 Table 32. Port 2 Control 3 26 RTL8309SB Datasheet Default Default ...
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... Address [15:8] 52.0 Switch MAC 53.7~ Switch MAC Address Byte 0. Address [7:0] 53.0 Single-chip 9-port 10/100Mbps Switch Controller VLAN Entry [C] Table 33. Port 2 Control 4 VLAN Entry [C] Switch MAC Address 27 RTL8309SB Datasheet Default 0000 0100 Default 0010 111 1 0000 0010 1111 0000 0x52 ...
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... Enable Diffserv priority classification Disable port- 55.0 1: Disable port priority function based priority 0: Enable port priority function. Ingress packets from port 3 will be classified as high priority Single-chip 9-port 10/100Mbps Switch Controller Table 35. Port 3 Control 0 Table 36. Port 3 Control 1 28 RTL8309SB Datasheet Default Default 11 0 ...
Page 44
... This register along with byte 60.7~60.0 defines the IEEE 802.1Q 12-bit [11:8] 61.0 VLAN identifier of VLAN D. Single-chip 9-port 10/100Mbps Switch Controller Table 37. Port 3 Control 2 Table 38. Port 3 Control 3 VLAN Entry [D] Table 39. Port 3 Control 4 VLAN Entry [D] 29 RTL8309SB Datasheet Default 1111 1000 Default 1111 ...
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... ISP MAC address byte 4. 64.7~64.0 ISP MAC address byte 3. 65.7~65.0 ISP MAC address byte 2. 66.7~66.0 ISP MAC address byte 1. 67.7~67.0 ISP MAC address byte 0. Table 41. Port 4 Control 0 Table 42. Port 4 Control 1 30 RTL8309SB Datasheet Default 0x05 0x42 0x2F 0x21 0x91 0x5C Default 11 11 ...
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... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Single-chip 9-port 10/100Mbps Switch Controller Table 43. Port 4 Control 2 Table 44. Port 4 Control 3 VLAN Entry [E] Table 45. Port 4 Control 4 31 RTL8309SB Datasheet Default 1 1 Default 1111 1000 ...
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... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Single-chip 9-port 10/100Mbps Switch Controller VLAN Entry [E] Table 46. MII Port Control 0 Table 47. MII Port Control 1 VLAN Entry [I] 32 RTL8309SB Datasheet Default 0000 0100 1111 0000 Default ...
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... VLAN identifier of VLAN I. 6.3.4. CPU Port and WAN Port Name Byte.bit Description WAN Port 82.7~ Specifies the WAN port on the RTL8309SB. 82.4 1000=MII Port is WAN Port 0111=Port 7 is WAN Port 0101=Port 5 is WAN Port 0011=Port 3 is WAN Port 0001=Port 1 is WAN Port CPU Port 82 ...
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... Enable Diffserv priority classification Disable port- 84.0 1: Disable port priority function based priority 0: Enable port priority function. Ingress packets from port 5 will be classified as high priority Single-chip 9-port 10/100Mbps Switch Controller Table 50. Port 5 Control 0 Table 51. Port 5 Control 1 34 RTL8309SB Datasheet Default Default 11 0 ...
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... VLAN. VLAN Entry [F] This register along with byte 90.3~90.0 defines the IEEE 802.1Q 12- bit VLAN identifier of VLAN F. This register along with byte 89.7~89.0 defines the IEEE 802.1Q 12- bit VLAN identifier of VLAN F. 35 RTL8309SB Datasheet Default 1111 1000 Default 1111 ...
Page 51
... Enable 802.1p priority classification 1: Disable Diffserv priority classification for ingress packets on port 6 0: Enable Diffserv priority classification 1: Disable port priority function 0: Enable port priority function. Ingress packets from port 6 will be classified as high priority Table 57. Port 6 Control 2 Description 36 RTL8309SB Datasheet Default Default ...
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... E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. VLAN Entry [G] This register along with byte 98.3~98.0 defines the IEEE 802.1Q 12- bit VLAN identifier of VLAN G. This register along with byte 97.7~97.0 defines the IEEE 802.1Q 12- bit VLAN identifier of VLAN C. 37 RTL8309SB Datasheet Default 1111 ...
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... Enable 802.1p priority classification 1: Disable Diffserv priority classification for ingress packets on port 7 0: Enable Diffserv priority classification 1: Disable port priority function 0: Enable port priority function. Ingress packets from port 7 will be classified as high priority Table 62. Port 7 Control 2 38 RTL8309SB Datasheet Default Default ...
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... This register along with byte 105.7~105.0 defines the IEEE 802.1Q 12-bit [11:8] 106.0 VLAN identifier of VLAN H. Single-chip 9-port 10/100Mbps Switch Controller Table 63. Port 7 Control 3 VLAN Entry [H] Table 64. Port 7 Control 4 VLAN Entry [H] 39 RTL8309SB Datasheet Default 1111 1000 0000 Default 0111 ...
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... Half duplex operation When NWay is enabled, this bit reflects the result of auto- negotiation (Read only). When NWay is disabled, this bit is strap option ‘Force_Duplex’ and can be configured through SMI (Read/Write). 40 RTL8309SB Latch High until clear Self Clearing Track ID: JATR-1076-21 Rev. 1.4 Datasheet Default 0 ...
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... Not 10Base-TX half duplex capable RO RO The RTL8309SB will accept management frames with preamble suppressed. The RTL8309SB accepts management frames without preamble. 32 minimum preamble bits are required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as defined in the IEEE 802 ...
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... PHY 0 Register 4: Auto-Negotiation Advertisement Note: Whenever the link ability of the RTL8309SB is reconfigured, the auto-negotiation process should be executed again to allow the configuration to take effect. Table 67. PHY 0 Register 4: Auto-Negotiation Advertisement Reg.bit Name 4.15 Next Page 4.14 Acknowledge 4.13 Remote Fault 4.[12:11] Reserved 4 ...
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... RW/ 1: Soft reset. This bit is self-clearing SC If this bit is set to 1, the RTL8309SB will reset all registers in it except PHY registers and will not load configurations from EEPROM or strapping pins. Software reset is designed to provide a convenient way for users to change the configuration via SMI ...
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... Will not enable transmit flow control no matter what the auto negotiation result When the RTL8309SB receives a pause control frame, it has the ability to stop the next transmission of a normal frame until the timer is expired based on the auto negotiation result 0: Will not receive flow control no matter what the ...
Page 60
... The default DiffServ code point listed below will be considered as high priority code point if the DiffServ priority function is enabled. EF – 101110 AF – 001010, 010010, 011010, 100010 Network Control – 111000, 110000 0: The default DiffServ code point will be considered low priority 45 RTL8309SB Datasheet Default 0 0 Default 100 1 11 ...
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... Table 74. PHY 0 Register 22: Port 0 Control 0 Mode Description RW Reserved Perform ‘local loopback’, i.e. loop MAC’s RX back Normal operation RW 1: The switch will replace a NULL VID with a port VID (12 bits replacement for a NULL VID 46 RTL8309SB Datasheet Default 0 1 111111 0 1 111111 Default ...
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... VLAN tags from packets then add new tags to them. The inserted tag is the ingress port’s ‘Default tag’, which is indexed by port 0’s ‘Port-based VLAN index’. This is a replacement processing for tagged packets and an insertion for untagged packets. 47 RTL8309SB Datasheet Default 0 Pin Dis_VLAN_Pri ...
Page 63
... VLAN will be broadcast to ports specified in this field. Bit 0 stands for port 0, bit 1 stands for port 8. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Table 77. PHY 0 Register 25: VLAN Entry [A] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A. 48 RTL8309SB Datasheet Default 1111 1000 ...
Page 64
... IP address [B] is enabled. RW The switch will compare both the source and destination IP addresses of an incoming packet against the value, IP address [B] AND IP mask [B], to classify priority for the packet priority for IP address [B] is enabled. 49 RTL8309SB Datasheet Default 0xFFFF 0xFFFF Default 0xFFFF 0xFFFF Track ID: JATR-1076-21 Rev ...
Page 65
... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Table 81. PHY 1 Register 25: VLAN Entry [B] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN B. 50 RTL8309SB Datasheet Default 0001 111 1 0000 0010 Default ...
Page 66
... IP address [B] is enabled. RW The switch will compare both the source and destination IP addresses of an incoming packet against the value, IP address [B] AND IP mask [B], to classify priority for the packet priority for IP address [B] is enabled. 51 RTL8309SB Datasheet Default 0xFFFF 0xFFFF Default 0xFFFF 0xFFFF Track ID: JATR-1076-21 Rev ...
Page 67
... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Table 85. PHY 2 Register 25: VLAN Entry [C] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN C. 52 RTL8309SB Datasheet Default 0010 111 1 0000 0100 Default ...
Page 68
... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Table 88. PHY 3 Register 25: VLAN Entry [D] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN D. 53 RTL8309SB Datasheet Default 0x5452 0x834C 0xB009 Default 0011 ...
Page 69
... ISP MAC Address Byte 1. 16.[7:0] = ISP MAC Address Byte 0. RW 17.[15:8] = ISP MAC Address Byte 3. 17.[7:0] = ISP MAC Address Byte 2. RW 18.[15:8] = ISP MAC Address Byte 5. 18.[7:0] = ISP MAC Address Byte 4. 54 RTL8309SB Datasheet Default 0x4205 0x212F 0x5C91 Track ID: JATR-1076-21 Rev. 1.4 ...
Page 70
... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Table 91. PHY 4 Register 25: VLAN Entry [E] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN E. 55 RTL8309SB Datasheet Default 0100 111 1 0001 0000 Default ...
Page 71
... VLAN tags from packets then add new tags to them. The inserted tag is the ingress port’s ‘Default tag’, which is indexed by MII port’s ‘Port-based VLAN index’. This is a replacement processing for tagged packets and an insertion for untagged packets. 56 RTL8309SB Datasheet Default ...
Page 72
... Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN I. Mode Description RW Specify the WAN port on the RTL8309SB. 1000=MII Port is WAN Port 0111=Port 7 is WAN Port 0101=Port 5 is WAN Port 0011=Port 3 is WAN Port 0001=Port 1 is WAN Port RW Specify the CPU port on the RTL8309SB. ...
Page 73
... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Table 97. PHY 5 Register 25: VLAN Entry [F] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN F. 58 RTL8309SB Datasheet Default 0101 111 1 0010 0000 Default ...
Page 74
... This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 46. Note: Reg 22.8 is not pin Sel_PortPri strap option for port 6. Default value for 22 7.7.7. PHY 6 Register 23: Port 6 Control 1 This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 48. Single-chip 9-port 10/100Mbps Switch Controller 59 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
Page 75
... VLAN will be forwarded to ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN. Table 99. PHY 6 Register 25: VLAN Entry [G] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN G. 60 RTL8309SB Datasheet Default 0110 111 1 0100 0000 Default ...
Page 76
... Command execution 16.0 Read or write operation Single-chip 9-port 10/100Mbps Switch Controller Mode Description RW 1: Trigger a command to read or write the lookup table 0: Indicates this command has completed RW 1: Read cycle 0: Write cycle 61 RTL8309SB Datasheet Default 1111 1111 1111 Track ID: JATR-1076-21 Rev. 1.4 ...
Page 77
... Membership’. Port 7 can only communicate within the membership. This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID. 62 RTL8309SB Datasheet Default 0x00 0x00 ...
Page 78
... RO 0: Normal operation (permanently= Full duplex operation 0: Half duplex operation When NWay is enabled, this bit reflects the result of auto- negotiation (Read only). When NWay is disabled, this bit may be set through SMI (Read/Write). 63 RTL8309SB Datasheet Default 1 1000 0000 Default 1111 0000 0000 ...
Page 79
... Next Page disabled (Permanently=0) RO Permanently Advertises that the RTL8309S has detected a remote fault 0: No remote fault detected Advertises that the RTL8309SB possesses 802.3x flow control capability 0: No flow control capability RO Technology not supported (Permanently=0 100Base-TX full duplex capable 0: Not 100Base-TX full duplex capable ...
Page 80
... If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=0, Reg4.5=1, the RTL8309SB will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=0. If the CPU polls register 5, the RTL8309SB replies with the contents in register 4. If the CPU polls register 4, the RTL8309SB replies with the contents in register 4. ...
Page 81
... By default, the RTL8309SB advertises full capabilities (100Full, 100Half, 10Full, 10Half) together with flow control ability. If the link partner to the RTL8309SB is forced to bypass auto negotiation, or auto negotiation is not supported, the link status of the RTL8309SB is determined by observing the signal at the receiver. ...
Page 82
... Power Saving Mode In power saving mode, the power for the MAC and parts of the PHY transceiver are turned off. The RTL8309SB implements power saving mode on a per-port basis. A port automatically enters power saving mode 10 seconds after the cable is disconnected from it. Once a port enters power saving mode, it transmits normal link pulses only on its TXOP/TXON pins and continues to monitor the RXIP/RXIN pins to detect incoming signals, which might be the 100Base-TX MLT-3 idle pattern, 10Base-T link pulses, or Auto-Negotiation’ ...
Page 83
... Otherwise, the RTL8309SB will broadcast the packet. This is the ‘Address Search’. The RTL8309SB then extracts the least 10 bits of the source MAC address to index the 1024-entry look-up table. If the entry is not already in the table it will record the source MAC address and add switching information. If this is an occupied entry, it will update the entry with new information. This is called ‘ ...
Page 84
... RTL8309SB sends a ‘pause off’ frame with zero pause time to turn on transmissions. On the receive side, when the RTL8309SB receives a pause control packet on a port, it stops transmitting any packets to this port, except flow control packets, for a period of time specified in the received pause control frame receives another pause control packet in this period of time on the same port, the timer will be updated with the new value specified in the latest pause control packet ...
Page 85
... By deferring, the RTL8309SB sends preambles to defer other stations’ transmissions. To avoid jabber and excessive deference as defined in IEEE 803.3, the RTL8309SB will pull down the carrier sense signal for a short time and then raise quickly. This short silence time is to prevent other stations seizing the medium and sending packets out. If there are packets to send out during the carrier sense rising up period, carrier sense flow control will be replaced by those packets ...
Page 86
... PHY mode. Refer to Figure 4, on page 72 to check the relationship between the RTL8309SB and the external device. Note: Connect the input of the RTL8309SB to the output of the external device. The RTL8309SB has no RXER, TXER, and CRS pins for MII signaling. Because the RTL8309SB does not support pin CRS necessary to connect the MTXEN/PRXDV (output) of PHY mode to both CRS and RXDV (input) of the external device ...
Page 87
... HomePNA/ RXDV Single PHY 4 RXD[3:0] TXC TXEN 4 TXD[3:0] COL 25M/2.5MHz RXC CPU/ CRS Processor/ RXDV 4 Routing Engine RXD[3:0] TXC TXEN 4 TXD[3:0] COL 10MHz RXC CPU/ CRS Processor/ RXDV 1 Routing Engine RXD TXC TXEN 1 TXD COL Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
Page 88
... RTL8309SB provides PHY register 0, 1, and 4, to virtually provide the MII port’s PHY status to the external MAC. Because the MII port of the RTL8309SB does not have a true PHY in it, it does not process the auto negotiation. The contents of PHY registers 4 and 5 should be the same for both terminals of the MII bus when operating on the same link status. Thus, the RTL8309SB does not provide PHY register 5 ...
Page 89
... These nine groups of VLAN membership registers, VLAN ID [A] membership bit [8:0] ~ VLAN ID [I] membership bit [8:0], determine which ports are members of this VLAN. The RTL8309SB forwards frames to members of this VLAN only (excluding the input port of this frame). VLAN membership registers descript which port are members in a VLAN member set. ...
Page 90
... VLAN function has higher priority than the trunking operation. The packet will not be forwarded to the port of this trunk. For non-VLAN tagged frames, the RTL8309SB performs port-based VLAN. It will use Port n VLAN index [3:0] to index to a VLAN membership. The VLAN ID associated with this indexed VLAN membership is the Port VID (PVID) of this port. ...
Page 91
... VLAN corresponding to the registers defined in VLAN ID [A] [11:0] ~ VLAN ID [I] [11:0]. If the VID of a VLAN-tagged frame does not hit the VLAN ID [A] [11:0] ~ VLAN ID [I] [11:0], then the RTL8309SB performs port-based VLAN mapping to the member set indexed by the Port n VLAN index [3:0]. Otherwise, the RTL8309SB compares the explicit identifier in the VLAN tag with the nine VLAN registers to determine the VLAN association of this frame, then forwards it to the member set of this VLAN ...
Page 92
... Point (DSCP) priority information from the DS-field defined in RFC2474. The DS field byte for the IPv4 is a Type-of-Service (TOS) octet. The recommended DiffServ Code Point is defined in RFC2597 to classify the traffic into different service classes. The RTL8309SB extracts the codepoint value of DS-fields from IPv4 packets and identifies the priority of the incoming IP packet following the definition below: High priority: where the DS-field = (EF, Expected Forwarding:) 101110 Differential service code point [A] specified in internal register ...
Page 93
... In Type 10, if Null VID replacement is enabled, this function has higher priority than type 10. If both type 10 is selected and Null VID replacement is enabled, the RTL8309SB inserts a PVID to non-tagged packets and replaces a null VID with a PVID for tagged packets, and does nothing in tagged packets with a non-null VID. ...
Page 94
... The RTL8309SB also provides the option to set port 6 and port trunk by configuring the ‘trunking port assignment’ bit in the internal register. ...
Page 95
... MAC WAN In the inbound process, when the RTL8309SB receives a packet from the WAN port, it will be directly forwarded to the CPU port according to the VLAN 1 configuration. The CPU looks up the mapping table to reverse translate the destination MAC address from the ISP MAC to the MAC address of the station G NIC. Figure 8 illustrates this inbound process. ...
Page 96
... SMI master mode (MDC is output) to control the state of PHY, and in SMI slave mode (MDC is input) to control the internal register. MDC is an input clock for the RTL8309SB to latch MDIO on its rising edge. The clock can run from 0MHz to 25MHz. MDIO is a bi-directional signal that is used to write data to, or read data from, the RTL8309SB. Table 111 shows the read and write cycle format of the RTL8309SB ...
Page 97
... Broadcast Input Drop Forwards any broadcast packet to any output port and will drop packets at the source port directly. Although this function effectively reduces the loading on the RTL8309SB, packets broadcast to non-congested ports will also be dropped. Broadcast Output Drop Only forwards broadcast packets to non-congested ports. But if a dropped packet is re-transmitted by a higher protocol in the congested port, the non-congested port will receive duplicate packets ...
Page 98
... Random Read: A random read requires a ‘dummy’ byte write sequence to load in the data word address. Sequential Read: For the RTL8309SB, the sequential reads are initiated by a random address read. After the 24LC02 receives a data word, it responds with an acknowledgement. As long as the 24LC02 receives an acknowledgement, it will continue to increment the data word address and clock out sequential data words in series ...
Page 99
... The RTL8309SB incorporates an advanced mechanism to prevent Head-Of-Line blocking problems when flow control is disabled. When the flow control function is disabled, the RTL8309SB first checks the destination address of the incoming packet. If the destination port is congested, the RTL8309SB will discard this packet to avoid blocking the next packet, which is going to a non-congested port. ...
Page 100
... The RTL8309SB provides a MAC loopback function on the MII port to detect cable problems or far end existence. When this function is enabled, the RTL8309SB will forward local and broadcast packets from the input of the MII port to the output of the MII port, and drop unicast packets from the input of the MII port. The other port can still forward broadcast or unicast packets to the MII port ...
Page 101
... Switch2 via Link1, then returned to Switch1 via Link2. When the loop detection function is enabled, the RTL8309SB periodically sends out a broadcast packet every 3~5 minutes and automatically detects whether there is a network loop (or bridge loop loop is detected the LoopLED# will be ON (active low or high) ...
Page 102
... Each pin may have different indicator meanings set by pins LED_MODE[2:0]. Refer to the pin descriptions for details (see Port LED Pins, on page 9). Upon reset, the RTL8309SB supports chip diagnostics and LED functions by blinking all LEDs once for 320ms. This function can be disabled by asserting EN_RST_BLNK to 0. LED_BLNK_TIME determines the LED blinking period for activity and collision (1 = 43ms and 0 = 120ms) ...
Page 103
... Speed Link/Act Flash 1 Flash Yellow Speed LED Green Yellow LED Green 88 RTL8309SB Datasheet Speed:Input=Pull-down, Active High. Bi-Color Link/Act: the active status of LED_ADD is the opposite of LED_SPD and does not interact with input upon reset. Speed Link/Act Flash 0 Flash Link/Act LED Speed LED Track ID: JATR-1076-21 Rev ...
Page 104
... Bi-color LED Speed LED BJT Single-chip 9-port 10/100Mbps Switch Controller Strapping Low 0.5K Link/Act Speed LED LED BJT 50 Figure 19. Bi-Color LED Reference Schematic 89 RTL8309SB Datasheet 7.5 ~12V 0.5K 0.5K Bi-color LED Link/Act LED BJT BJT Track ID: JATR-1076-21 Rev. 1.4 ...
Page 105
... Peak continuous 100% utilization Power saving Power down 10Base-T, idle 10Base-T, Peak continuous 100% utilization 100Base-TX, idle 100Base-TX, Peak continuous 100% utilization Power saving Power down VDDIO = 1.8V VDDIO = 3.3V 90 RTL8309SB Datasheet Max Units °C +150 +2.16 V +3.00 V +3.96 V VDDD V ...
Page 106
... Percent of Vp+ or Vp- 10-90% of Vp Deviation from best-fit time-grid, 010101 … Sequence Idle pattern Transmitter, 10Base-T 50Ω from each output to Vcc, all pattern Period of time from start of TP_IDL to link pulses or period of time between link pulses 91 RTL8309SB Datasheet Min Typical Max Units - - 0 0.8 ...
Page 107
... Terminate each end with 50Ω resistive load. Return loss from 5MHz to 10MHz for reference resistance of 100 Ω. dB below fundamental, 20 cycles of all ones data cyc 92 RTL8309SB Min Typical Max 245 254 24.0 24.5 25.0 40.2 44.3 45.1 6.4 8.5 11.5 24 ...
Page 108
... MTXC/PRXC, MRXC/PTXC clock cycle time Output Setup time from REFCLK rising edge to MTXD[0]/PRXD[0], MTXEN/PRXDV, MCOL/PCOL Output Hold time from REFCLK rising edge to MTXD[0]/PRXD[0], MTXEN/PRXDV, MCOL/PCOL MTXD[0]/PRXD[0], MRXDV/PTXEN to REFCLK rising edge setup time 93 RTL8309SB Datasheet I/O Min Type Max Units I ns 40±50 ppm ...
Page 109
... SYM Junction operating Tj temperature Ambient operating Ta temperature Single-chip 9-port 10/100Mbps Switch Controller Condition MTXD[0]/PRXD[0], MRXDV/PTXEN to REFCLK rising edge hold time LED Timing Tc Figure 22. Cross-section of 128-Pin PQFP Table 119. Thermal Operating Range Condition 94 RTL8309SB Datasheet I/O Min Type Max Units 120 ...
Page 110
... Standalone 10/100 switch Small workgroup switch VoIP infrastructure switch Single-chip 9-port 10/100Mbps Switch Controller Table 120. Thermal Resistance Condition 2 layer PCB, 0 ft/s airflow, ambient temperature 25°C 2 layer PCB, 0 ft/s airflow, ambient temperature 25°C 95 RTL8309SB Datasheet Min Typical Max Units °C/W - 36.7 - °C ...
Page 111
... Design and Layout Guide In order to achieve maximum performance using the RTL8309SB, good design attention is required throughout the design and layout process. The following are some recommendations on how to implement a high performance system. General Guidelines • Provide a good power source, minimizing noise from switching power supply circuits (<50mV). ...
Page 112
... Transformer Options The RTL8309SB can use a transformer that supports auto MDIX with a 1:1 turn ratio on both transmit and receive paths. There are many venders improving their transformer design to meet the RTL8309SB’s requirement. The center taps on the primary side of the transmit and receive paths in the transformer should be connected together inside the transformer and provide one common external pin (Figure 23). This common pin should connect to 1.8V directly and connect to ground via a 0.1µ ...
Page 113
... Smith’ termination is often provided for the unused signal pairs of RJ-45 pins 4 & 5, and 7 & minimize the common mode noise induced from RJ-45 pins 1 & 2, and 3 & 6. Single-chip 9-port 10/100Mbps Switch Controller 1:1 1:1 75Ω 75Ω 0.1µF/3KV Chassis GND Figure 24. Bob Smith Termination 98 RTL8309SB Datasheet RJ- 75Ω ...
Page 114
... Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Single-chip 9-port 10/100Mbps Switch Controller 99 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet ...
Page 115
... APPROVE 22.90 23.20 23.50 0.68 0.88 1.08 1.35 1.60 1.85 CHECK - - 0.10 0° - 12° 100 RTL8309SB visual inspection. TITLE: -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: DOC. NO. VERSION PAGE DWG NO. DATE REALTEK SEMICONDUCTOR CORP. Track ID: JATR-1076-21 Rev. 1.4 Datasheet ...