MPC9350 Motorola, MPC9350 Datasheet

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MPC9350

Manufacturer Part Number
MPC9350
Description
LOW VOLTAGE PLL CLOCK DRIVER
Manufacturer
Motorola
Datasheet

Specifications of MPC9350

Case
BGA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
generator targeted for high performance clock distribution systems. With
output frequencies of up to 200 MHz and maximum output skews of 150
ps the MPC9350 is ideal for the most demanding clock tree designs. The
device offers 9 low skew clock outputs, each is configurable to support the
clocking needs of the various high-performance microprocessors
including the PowerQuicc II integrated communication microprocessor.
The extended temperature range of the MPC9350 supports
telecommunication and networking requirements. The devices employs a
fully differential PLL design to minimize cycle-to-cycle and long-term jitter.
Features
Functional Description
clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference
clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable
PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects
between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match
the VCO frequency range. With the available feedback output dividers the internal VCO of the MPC9350 is running at either 16x
or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one
eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD
pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal
oscillator inputs or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode
when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to
the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test
mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting
the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350 is
fully 2.5V and 3.3V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external
components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept LVCMOS signals while the
outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines, each of the MPC9350 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The
device is packaged in a 7x7 mm 2 32-lead LQFP package.
9 outputs LVCMOS PLL clock generator
25 – 200 MHz output frequency range
2.5V and 3.3V compatible
Compatible to various microprocessor such as PowerQuicc II
Supports networking, telecommunications and computer applications
Fully integrated PLL
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1
Oscillator or crystal reference inputs
Internal PLL feedback
Output disable
PLL enable/disable
Low skew characteristics: maximum 150 ps output-to-output
32 lead LQFP package
Temperature range –40 C to +85 C
The MPC9350 is a 2.5V and 3.3V compatible, PLL based clock
The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference
Motorola, Inc. 2002
Freescale Semiconductor, Inc.
For More Information On This Product,
1
Go to: www.freescale.com
W
transmission lines. For series terminated
CLOCK GENERATOR
3.3V AND 2.5V PLL
32 LEAD LQFP PACKAGE
MPC9350
LOW VOLTAGE
CASE 873A
FA SUFFIX
Order Number: MPC9350/D
Rev 3, 01/2002

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MPC9350 Summary of contents

Page 1

... The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350 is fully 2.5V and 3.3V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external components beyond a series resonant crystal ...

Page 2

... PLL_EN (pulldown) FSELA (pulldown) FSELB (pulldown) FSELC (pulldown) FSELD (pulldown) OE GND QB VCCO QA GND TCLK PLL_EN REF_SEL Figure 2. Pinout: 32–Lead Package Pinout (Top View) For More Information On This Product, MOTOROLA 0 2 PLL Ref 200 - 400 MHz Figure 1. MPC9350 Logic Diagram MPC9350 to: www.freescale.com ...

Page 3

... Positive power supply for I/O and core 0 Selects TCLK PLL enabled. The VCO output is routed to the output dividers 32 Selects feedback divider VCO = 16 * Input reference clock Outputs disabled VCO VCO VCO VCO Min -0.3 -0.3 -0.3 - to: www.freescale.com MPC9350 Function Max Unit Condition 125 C MOTOROLA ...

Page 4

... Maximum Quiescent Supply Current V TT Output termination voltage 1. The MPC9350 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage Alternatively, the device drives up to two 50 series terminated transmission lines. AC CHARACTERISTICS ( 3.3V Symbol ...

Page 5

... V TT Output termination voltage a. The MPC9350 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage Alternatively, the device drives up to two 50 series terminated transmission lines per output. For More Information On This Product, TIMING SOLUTIONS 5 – ...

Page 6

... Freescale Semiconductor, Inc. MPC9350 Programming the MPC9350 The MPC9350 clock driver outputs can be configured into several divider modes, in addition the internal feedback of the device allows for flexibility in establishing two input to output frequency relationships. The output division settings establish the output frequency relationship. The output divider of the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios ...

Page 7

... DC voltage drop that will be seen between the V CC supply and the V CCA pin of the MPC9350. From the data sheet the I VCCA current (the current sourced through the V CCA pin) is typically 10 mA (15 mA maximum), assuming that a minimum of 3.0V must be maintained on the V CCA pin ...

Page 8

... Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9350 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs ...

Page 9

... Freescale Semiconductor, Inc. PULSE GENERATOR Figure 7. TCLK MPC9350 AC test reference for 3.3V and 2.5V t SK(O) The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 8. Output–to–output Skew t SK(O) ...

Page 10

... Freescale Semiconductor, Inc. MPC9350 –T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD For More Information On This Product, MOTOROLA OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X 0.20 (0.008) AB T–U Z –U– 0.20 (0.008) AC T– ...

Page 11

... Freescale Semiconductor, Inc. For More Information On This Product, TIMING SOLUTIONS NOTES 11 Go to: www.freescale.com MPC9350 MOTOROLA ...

Page 12

... ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ For More Information On This Product, MOTOROLA 12 Go to: www.freescale.com MPC9350/D TIMING SOLUTIONS ...

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