SAA7140A Philips Semiconductors, SAA7140A Datasheet
SAA7140A
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SAA7140A Summary of contents
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... DATA SHEET SAA7140A; SAA7140B High Performance Scaler (HPS) Objective specification Supersedes data of 1996 Jul 26 File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1996 Sep 04 ...
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... Port I/O control; subaddress 21H 8.3.4 Register set A (02H to 1FH) and B (22H to 3FH) 9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 1996 Sep 04 SAA7140A; SAA7140B 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction 15.2 Reflow soldering 15.3 Wave soldering 15.3.1 QFP 15.3.2 SO 15.3.3 Method (QFP and SO) 15 ...
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... The devices resample digital video signals using two dimensional phase-correct interpolation in order to display arbitrarily sized window. The SAA7140A fits perfectly into signal environment and requires two different supply voltages (5 V and 3.3 V). The SAA7140B is a pure 3.3 V design and therefore has only 3 ...
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... Philips Semiconductors High Performance Scaler (HPS) 4 BLOCK DIAGRAMS 1996 Sep 04 SAA7140A; SAA7140B 4 Objective specification ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B 5 Objective specification ...
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... V) digital border supply voltage 6 (+5 V) digital border ground general purpose port 3 input/output (set via I general purpose port 2 input/output (set via I general purpose port 1 input/output (set via I 6 Objective specification SAA7140A; SAA7140B DESCRIPTION pixel rate); DMSD port 2 C-bus) 2 C-bus) 2 ...
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... VRAM port output (bit 18) 32-bit VRAM port output (bit 17) 32-bit VRAM port output (bit 16) 32-bit VRAM port output (bit 15) 32-bit VRAM port output (bit 14) 32-bit VRAM port output (bit 13) 32-bit VRAM port output (bit 12) 7 Objective specification SAA7140A; SAA7140B DESCRIPTION 2 C-bus) ...
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... Y bidirectional expansion port, high byte (bit 1) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 0) in 16-bit mode luminance component Y digital border supply voltage 12 (+ Objective specification SAA7140A; SAA7140B DESCRIPTION 2 C-bus ...
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... U and V pixel qualifier input signal to mark valid pixels; expansion port horizontal sync input signal; expansion port vertical sync input signal; expansion port line-locked system clock input/output; expansion port 9 Objective specification SAA7140A; SAA7140B DESCRIPTION ...
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... UVIN6 27 UVIN7 28 V DDD(bord SSD(bord)3 30 SDA 31 SCL 32 IICSA 33 V DDD(bord SSD(bord DDD(bord SSD(bord)5 37 PORT3 38 1996 Sep 04 SAA7140A Fig.3 Pin configuration (SAA7140A). 10 Objective specification SAA7140A; SAA7140B 102 VIO V SSD(bord)10 101 V DDD(bord)11 100 V SSD(bord DDD(bord) FDIO 96 VRO0 95 VRO1 94 VRO2 93 VRO3 92 VRO4 91 VRO5 ...
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... V) digital ground digital supply voltage 7 (+3.3 V) digital ground general purpose port 3 input/output (set via I general purpose port 2 input/output (set via I general purpose port 1 input/output (set via I 11 Objective specification SAA7140A; SAA7140B DESCRIPTION pixel rate); DMSD port 2 C-bus) 2 C-bus) 2 C-bus) ...
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... VRAM port output (bit 18) 32-bit VRAM port output (bit 17) 32-bit VRAM port output (bit 16) 32-bit VRAM port output (bit 15) 32-bit VRAM port output (bit 14) 32-bit VRAM port output (bit 13) 32-bit VRAM port output (bit 12) 12 Objective specification SAA7140A; SAA7140B DESCRIPTION 2 C-bus) ...
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... Y bidirectional expansion port, high byte (bit 1) in 16-bit mode luminance component Y bidirectional expansion port, high byte (bit 0) in 16-bit mode luminance component Y digital supply voltage 15 (+3 Objective specification SAA7140A; SAA7140B DESCRIPTION 2 C-bus ...
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... U and V pixel qualifier input signal to mark valid pixels; expansion port horizontal sync input signal; expansion port vertical sync input signal; expansion port line-locked system clock input/output; expansion port 14 Objective specification SAA7140A; SAA7140B DESCRIPTION ...
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... V SSD4 30 SDA 31 SCL 32 IICSA 33 V DDD6 34 V SSD5 35 V DDD7 36 V SSD6 37 PORT3 38 1996 Sep 04 SAA7140B Fig.4 Pin configuration (SAA7140B). 15 Objective specification SAA7140A; SAA7140B 102 VIO V SSD13 101 V DDD14 100 V SSD12 99 V DDD13 98 97 FDIO 96 VRO0 95 VRO1 94 VRO2 93 VRO3 92 VRO4 ...
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... Philips Semiconductors High Performance Scaler (HPS) 7 FUNCTIONAL DESCRIPTION The SAA7140A and SAA7140B accepts YUV data in a 16-bit wide parallel format at the DMSD port and accepts YUV input in a 16-bit wide parallel format and in an 8-bit byte-multiplexed Cb-Y-Cr-Y- format (CCIR-656 or D1 oriented) at the expansion port. ...
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... The signal is fixed to 0 (Register set A forced) or forced to 1 (Register set A forced). Fig.5 Field detection/register set mapping. The internal processing of the SAA7140A and SAA7140B relies on the presence of LLC, i.e. a clock of at least twice the sampling rate of the input data stream. The maximum LLC rate is 32 MHz ...
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... The sequence only increments with qualified bytes. 1996 Sep 04 SAA7140A; SAA7140B Instead of a vertical sync signal, as described for the DMSD port, the expansion port also supports an odd/even signal applied to the input pin VIN or VIO (controlled by ...
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... Fig.6 Timing of PXQIN for 16-bit data input from DMSD to expansion port. handbook, full pagewidth LLC CREF PXQIN Cb VIDL7 to 0 HIN Fig.7 Timing of PXQIO for serial 8-bit data input at expansion port. 1996 Sep 04 Cr0 Objective specification SAA7140A; SAA7140B Cb2 Cr2 MHA130 MHA126 ...
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... LLC CREF PXQIO VIDL7 to 0 Cb0 VIDH7 HIO Fig.9 Timing of PXQIO for non-zoomed 16-bit data output at expansion port. 1996 Sep 04 00H 00H SAV FFH Cr0 Cb2 Objective specification SAA7140A; SAA7140B Y Cr 00H 00H EAV MHA129 Cr2 Y3 MHA127 ...
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... Fig.10 Timing of PXQIN for zoomed 16-bit data output at expansion port. handbook, full pagewidth LLC CREF PXQIO VIDL7 HIO Fig.11 Timing of PXQIO for serial 8-bit data output at expansion port. 1996 Sep 04 Cr0 Cb2 Cr2 Cb4 Objective specification SAA7140A; SAA7140B Cr4 Cb6 Cr6 MHA128 MHA131 ...
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... C-bus The chrominance signal can be controlled via the I using bits SAT6 to SAT0. For the saturation control: 00H = colour off 40H = nominal gain of 1.0 7FH = maximum gain of 1.9999. 22 Objective specification SAA7140A; SAA7140B ACTIVE VIDEO WINDOW SCALING WINDOW line PXQV HGTV HIN/HREF ...
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... XPSC > 8, > 6 and >32, which reduces the input signal quantization. In addition, for XPSC the CXY and CXUV parameter become valid. 2 C-bus bits PFY3 to 0 and 23 SAA7140A; SAA7140B 2 C-bus settings. Subsampler 1 down to icon size, a FIR filtering subsampler is 2 equalling the number of input pixel/line and N ...
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... I C-bus bytes PFU3 to PFU0. (1) = 0001; (2) = 0010; (3) = 1010; (4) = 1110; (5) = 0011; (6) = 1111. Fig.14 Chrominance prefilter frequency response for miscellaneous I 1996 Sep 04 0.2 0.3 (5) (6) 0.2 0.3 24 Objective specification SAA7140A; SAA7140B MHA121 (1) (2) (3) (5) (4) 0.4 0 clk 2 C-bus settings. MHA122 (1) (2) (4) (3) ...
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... SAA7140A; SAA7140B WEIGHT DCGX SUM (HEX ...
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... BCS control. = number of OL Normally the weighting would this 2 C-bus situation the gain can be renormalized with DCGY2 to DCGY0 = 010 (factor Table 2 gives examples for I depending on a given scale ratio. 26 Objective specification SAA7140A; SAA7140B WEIGHT DCGX SUM ...
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... Objective specification SAA7140A; SAA7140B = 2 (dotted lines) (1-S)} = 682 = INT{YSCI/16 MHA120 CYB WEIGHT DCGY (HEX) SUM ...
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... AD 1211 2121 1211 1 ; IC-bus linear phase 2 handbook, halfpage = number SAA7140A; SAA7140B CYB WEIGHT DCGY (HEX) SUM ...
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... Interpolation into RGB data in accordance with CCIR 601 recommendations. 29 Objective specification SAA7140A; SAA7140B of the pixel distance. 2 C-bus parameters XSCI and XP the fine scalers input pixel count, XSCI 4 = number of input pixels per line (at SAA7140A = number of desired output pixels/line 1024 IP INT = ---------- - --------------------------------- - N XPSC ...
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... At the falling or rising edge of VSYV the FLDV output is stable. 30 Objective specification SAA7140A; SAA7140B 24-bit RGB: code 16 for black and code 235 for full saturation. codes black with 00H and white with FFH. This representation can be achieved by corresponding programming of brightness (equals offset), contrast and saturation (equals gain) in the YUV domain ...
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... PIXCLK line vertical blanking last half-full request for line n (1) 64LLC 64LLC (1) line increment sequence (1) 10LLC vertical reset pulse Fig.18 Vertical reset timing of the VRAM port. 31 Objective specification SAA7140A; SAA7140B transfer cycle (8 VCLK cycles minimum set-up time MHA123 MHA132 ...
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... Is dynamic field-wise switching required or is the source switching quite static, if static then do not be confused about odd or even; use SREGS and IREGS before referring to the I 32 Objective specification SAA7140A; SAA7140B 2 C-bus bit SRIO = 0 2 C-bus bit FLDC = 1 and use of 2 C-bus bit 2 C-bus section ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B 33 Objective specification ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B 34 Objective specification ...
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... Monochrome format (see Tables 6 and 7); If TTR = 1 and FS2 = 1 then Ya = Yb. 7.8.3 To reduce the power consumption of the SAA7140A and SAA7140B during phases, where no scaling operations are requested in the application possible to switch the SAA7140A and SAA7140B into a pseudo sleep mode. This mode can be activated, if the clock input LLCIN is not used or if the hardware is able to pull the LLCIN input or the LLCIO pin (in input mode) down to logic 0 ...
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... Sep 04 To activate the scaler again, switch back to an active input clock, via SRIO and/or LLCS. In ‘Sleep Mode’ the power consumption of the SAA7140A and SAA7140B is reduced to approximately 15% of its 2 C-bus normal operational value. ...
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... RGB and YUV = digital signals odd pixel numbers even pixel numbers and d = consecutive pixels. 1996 Sep 04 FS1 = 0; FS0 = 1 YUV (1)(2) (2)(3)(4) 32-BIT WORDS Objective specification SAA7140A; SAA7140B FS1 = 1; FS0 = 0 FS1 = 1; FS0 = 1 YUV 8-BIT MONOCHROME (2) 16-BIT WORDS 32-BIT WORDS OUTPUT NOT USED C-bus), ( ...
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... B0 B0 Notes 1. = keying bit. 2. RGB and YUV = digital signals even pixel numbers and b = consecutive pixels. 1996 Sep 04 FS1 = 0; FS0 = 1 YUV (1)(2) (2)(3) 16-BIT WORDS Objective specification SAA7140A; SAA7140B FS1 = 1; FS0 = 0 FS1 = 1; FS0 = 1 RGB ( 8-BIT MONOCHROME (2) 24-BIT WORDS 16-BIT WORDS C-bus), ( ...
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... VRO7 VRO6 ( ( VRO5 ( ( VRO4 ( ( VRO3 ( ( VRO2 ( ( VRO1 ( ( VRO0 ( ( Notes 1. = keying bit. 2. RGB = digital signals. 1996 Sep 04 FS1 = 0; FS0 = 1 YUV (1)(2) (1)(2) 16-BIT WORDS Objective specification SAA7140A; SAA7140B FS1 = 1; FS0 = 0 FS1 = 1; FS0 = 1 RGB ( 8-BIT MONOCHROME (1)(2) 24-BIT WORDS 16-BIT WORDS C-bus), ( ...
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... VRO16 B0 Z Notes 1. = keying bit. 2. RGB and YUV = digital signals high ohmic (3-state even pixel numbers and b = consecutive pixels. 1996 Sep 04 FS1 = 0, FS0 = 1 YUV (1)(2)(3) 32-BIT LONG WORD Objective specification SAA7140A; SAA7140B FS1 = 1, FS0 = 1 8-BIT MONOCHROME (2)(4) 32-BIT LONG WORD ...
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... RGB and YUV = digital signals high ohmic (3-state odd pixel numbers even pixel number and d = consecutive pixels. 1996 Sep 04 FS1 = 0, FS0 = 1 YUV (1)(2)(3) 32-BIT LONG WORD Objective specification SAA7140A; SAA7140B FS1 = 1, FS0 = 1 8-BIT MONOCHROME (2)(3)(4)(5) 32-BIT LONG WORD ...
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... Table 12 I C-bus status byte (X in address byte = 1; 71H at IICSA = LOW or 73H at IICSA = HIGH) FUNCTION Status byte (subaddress 20H) Table 13 Function of status bits ID3 to ID0 (software model of SAA7140A and SAA7140B compatible) ID3 0 Remark: With the exception of subaddress 20H (read only) all I ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B 43 Objective specification ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B 44 Objective specification ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B 45 Objective specification ...
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... Sep 04 DMSD ; PORT SUBADDRESS field sequence as detected from H and V sync signals field sequence synchronized to H and V but noise limited free running field sequence reserved DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 46 Objective specification SAA7140A; SAA7140B 00H DESCRIPTION ...
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... DESCRIPTION DESCRIPTION 47 Objective specification SAA7140A; SAA7140B BITS REMARK pixel 1 pixel 1 FS2 = 0; TTR = 0 pixel 0 pixel 0 ...
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... Note 1. The qualifier output on PXQIO may be disabled by I 1996 Sep 04 DESCRIPTION DESCRIPTION 21H DESCRIPTION DESCRIPTION 1FH) B (22H 3FH) AND TO DESCRIPTION 2 C-bus bits SRIO = 1 and LLCS = 1; see Table 37. DESCRIPTION 2 C-bus bits SRIO = 1 and VIPSI = 1; see Table 38. 48 Objective specification SAA7140A; SAA7140B ...
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... FDIO may be provided with a 7196 DIR like signal and is switched to input LLCIO, PXQIO and VIDH/VIDL I/O definition as defined by the I selected outputs are forced to input mode and corresponding signals are used as scaler input 49 Objective specification SAA7140A; SAA7140B DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 2 ...
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... VS from DMSD port; VS and HREF for field detection source is VIN from expansion port; VIN and HIN for field detection source is VIO from expansion port; VIO and HIO for field detection DESCRIPTION 50 Objective specification SAA7140A; SAA7140B DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
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... VRAM output + transparent format DESCRIPTION DESCRIPTION 51 Objective specification SAA7140A; SAA7140B OUTPUT FORMAT 16-bit/pixel; 32-bit word length; RGB matrix on, 8-bit/pixel; 32-bit word length; RGB matrix off, 16-bit/pixel; 16-bit word length; RGB matrix on, 16-bit/pixel; 16-bit word length; RGB matrix off; ...
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... ... ... ... ... ... ... ... ... ... ... ... ... Objective specification SAA7140A; SAA7140B D1 D0 GAIN 1 1 255 (bright) ... ... 0 0 128 (CCIR level) ... ... (dark GAIN 1 1 1.999 (maximum contrast) ... ... (CCIR level) ... ... (luminance off GAIN 1 1 1.999 (maximum contrast) ...
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... N (XPSC) = TRUNC [ number of qualified scaler input pixel IN 1996 Sep 04 DESCRIPTION DESCRIPTION DESCRIPTION distance between 2 pixels) PXQ PXQ DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION distance between 2 lines) LINE LINE DESCRIPTION ⁄ (XPSC + 1 number of prescaler output pixel and Objective specification SAA7140A; SAA7140B ...
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... YACL has to fit to the vertical scaling factor (defined by YSCI9 to YSCI0) 1996 Sep 04 DESCRIPTION DESCRIPTION DESCRIPTION PFY0 H1(z) 0 bypass 1 active 0 active 1 active H1(z) 0 bypass 1 active 0 active 1 active DESCRIPTION 54 SAA7140A; SAA7140B H2(z) bypass bypass bypass active and H2(z) bypass bypass active active and Objective specification H3(z) bypass bypass active ...
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... The weighting/gain factor is given in Table 72. Table 72 Weighting factor as a function of gain factor CYI DCGY0 DCGY1 1996 Sep 04 DESCRIPTION DESCRIPTION CYAi DCGY1 DCGY0 .... .... .... .... 1 1 DCGY2 DCGY3 Objective specification SAA7140A; SAA7140B CYi WEIGHTING FACTOR DCGY GAIN FACTOR 0 1 .... .... 7 DCGY4 DCGY5 DCGY6 CYBi + CYAi .... .... 256 DCGY7 ...
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... VL3 VL2 VL1 VL0 Objective specification SAA7140A; SAA7140B DCGX0 DESCRIPTION as maximum negative value = 128 signal level limit = 0 as maximum positive value = +127 signal level DESCRIPTION as maximum negative value = 128 signal level limit = 0 as maximum positive value = +127 signal level GAIN ...
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... SAA7140A SAA7140A SAA7140B SAA7140B SAA7140B SAA7140A SAA7140B PARAMETER 57 SAA7140A; SAA7140B DESCRIPTION as maximum negative value = 128 signal level limit = 0 as maximum positive value = +127 signal level DESCRIPTION as maximum negative value = 128 signal level limit = 0 as maximum positive value = +127 signal level CONDITIONS MIN ...
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... SAA7140B data clocks 3-state I/O; high-impedance state all outputs; SAA7140A clocks; SAA7140B clocks; SAA7140A clocks; SAA7140B other outputs; SAA7140A other outputs; SAA7140B other outputs; SAA7140B 58 Objective specification SAA7140A; SAA7140B = unless otherwise specified. amb MIN. TYP. MAX. 4.5 5 ...
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... DDD CONDITIONS LLCH LLC note 2 note 3 note 3 0 0.85V DDD 0.85V to 0.6 V DDD LLCIOH LLCIO 0 0.85V DDD 0.85V to 0.6 V DDD 59 Objective specification SAA7140A; SAA7140B MIN. TYP. 0.5 +1.5 0.5 0.3V 0.7V V DDD unless otherwise specified. amb MIN. TYP ...
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... CONDITIONS VRO outputs other outputs pF; note pF; notes 6 and pF; note pF; note pF; note pF; notes 6 and pF; note pF; note pF; note pF; note pF; note zooming may be infinite. 60 Objective specification SAA7140A; SAA7140B MIN. TYP. MAX 1 7 810 840 . During a VRAM transfer, the falling edge Scaler UNIT ...
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... VOEN VCLK t enVRO not valid DATA OUTPUT VRAM port OUTPUT HFL 1996 Sep 04 T VCLK odVRO t ohVRO Fig.19 Data output timing (VRAM port). 61 Objective specification SAA7140A; SAA7140B 2.4 V 1.5 V 0.6 V 2.4 V 1 odVRO 0.85V DD 0.4 V 0.85V DD 0.4 V MHA125 ...
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... EXPANSION PORT CLOCK OUTPUT LLCIO Fig.20 Data input/output timing (DMSD port and expansion port). 1996 Sep 04 T LLC , T LLCIN t LLCH , t LLCINH LLCIOH Objective specification SAA7140A; SAA7140B t r not valid LLCIOL t r 2.4 V 1.5 V 0.6 V 2.4 V 0.6 V 2.4 V 0.6 V 0.85V DD 0.4 V ...
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... Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT425-1 1996 Sep scale (1) ( 0.27 0.20 20.1 14.1 22.15 16.15 0.5 0.17 0.09 19.9 13.9 21.85 15.85 REFERENCES JEDEC EIAJ 63 SAA7140A; SAA7140B detail 0.75 0.70 1.0 0.2 0.12 0.45 0.58 EUROPEAN PROJECTION Objective specification SOT425 ...
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... This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Sep 04 SAA7140A; SAA7140B If wave soldering cannot be avoided, the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1996 Sep 04 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 65 Objective specification SAA7140A; SAA7140B 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B NOTES 66 Objective specification ...
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... Philips Semiconductors High Performance Scaler (HPS) 1996 Sep 04 SAA7140A; SAA7140B NOTES 67 Objective specification ...
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... Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. + 24825 © Philips Electronics N.V. 1996 All rights are reserved ...