TMP91C829F TOSHIBA Semiconductor CORPORATION, TMP91C829F Datasheet
TMP91C829F
Specifications of TMP91C829F
Related parts for TMP91C829F
TMP91C829F Summary of contents
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... Micro controller TLCS-900/L1 series TMP91C829F REV1.2 September 7, 2001 Data Book ...
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... TLCS-900/L1 Devices TMP91C829F 1. OUTLINE AND DEVICE CHARACTERISTICS 2. PIN ASSIGNMENT AND PIN FUNCTIONS 3. OPERATION 3.1 CPU 3.2 Outline of Operation Modes 3.3 Memory Map 3.4 Triple Clock Function and Standby Function 3.5 Interrupts 3.6 Ports Functions 3.7 Chip Select/Wait Controller 3.8 8-bit Timers (TMRA) 3 ...
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REV PAGE Modification Item 1.2 169 Serial Channel Timing modified “14X”→”16X” ...
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... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. UNDERDEVELOPMENT CMOS 16-Bit Microcontrollers TMP91C829F 91C829-1 TMP91C829 980508TBA1 ...
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AD converter: 8 channels (9) Watchdog timer (10) Chip Select/Wait controller: 4 blocks (11) Interrupts: 33 interrupts 9 CPU interrupts: Software interrupt instruction and illegal instruction 17 internal interrupts: 7 priority levels are selectable. 7 external interrupts: 7 ...
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ADTRG(AN3/PA3) AN0∼AN7(PA0∼PA7) 10-BIT 8CH VREFH A/D VREFL CONVERTER AVCC AVSS PORT PORT Z PZ2(HWR) PZ3 TXD0(P80) RXD0(P81) SERIAL I/O SCLK0/CTS0(P82) (CH. 0) STS0(P83) TXD1(P84) SERIAL I/O RXD1(P85) (CH. 1) SCK1/CTS1(P86) STS1(P87) PORT 8 8BIT TIMER TA0IN/INT1(P70) (TIMER0) ...
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... PIN ASSIGNMENT AND PIN FUNCTIONS The assignment of input/output pins for the TMP91C829F, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1 shows the pin assignment of the TMP91C829F. PIN ASSIGNMENT DIAGRAM 端子名 Pin No. P27/A23 64 P26/A22 65 P25/A21 66 P24/A20 ...
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Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2 Pin names and functions. Number Pin Name I/O of Pins I/O P10 to P17 8 I/O D8 ...
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Number Pin Name I/O of Pins P73 1 TA4IN INT3 P74 1 TA5OUT P75 1 INT4 P80 1 TXD0 P81 1 RXD0 P82 1 SCLK0 CTS 0 P83 1 STS0 P84 1 TXD1 P85 1 RXD1 P86 1 SCLK1 CTS ...
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Number Pin Name I/O of Pins BOOT 1 1 NMI AM0 RESET VREFH 1 VREFL 1 AVCC 1 AVSS 1 X1/X2 2 HVCC 2 LVCC 2 DVSS 3 EMU0 1 EMU1 1 Note: An external DMA ...
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Operation This section describes the basic components, functions and operation of the TMP91C829. Notes and restrictions which apply to the various items described here are outlined in Section 7. Precautions and Restrictions at the end of this databook. 3.1 ...
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FPH sampling RESET A23 CS0 1 3 CS2 DATA- DATA-OUT WR HWR Note: Pull-up (internal) High-z sampling (After reset released, startting 2 wait read cycle) (PZ2 input mode) ...
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Outline of Operation Modes There are multi-chip and multi-boot modes. Which mode is selected depends on the device’s pin state after a reset. Multi-chip mode: The device nomally operations in this mode. After a reset, the device starts executing ...
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... Memory Map Figure 3.3 memory map of the TMP91C829F. Multi-chip Mode 000000H Internal I/O (4 Kbytes) 000100H 001000H Internal RAM (8 Kbytes) 003000H External memory 01F800H Internal boot ROM (2 Kbytes) 01FFFFH External memory FFFF00H Vector table (256 bytes) FFFFFFH Figure 3.3.1 TMP91C829 Memory Map ...
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Triple Clock Function and Standby Function The TMP91C829 contains (1) a clock gearing system, (2) a standby controller and (3) a noise-reducing circuit used for low-power, low-noise systems. The clock operating mode is as follows: (a) Single ...
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Block diagram of system clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> Warming up timer (High frequency oscillator) X1 High-Frequency oscillator f X2 OSCH f SYS T0 Figure 3.4.2 Block Diagram of System clock Under development fc fc/2 fc/4 fc/8 fc/ ...
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SFR 7 SYSCR0 Bit symbol (00E0H) Read/Write After reset 1 Always Always Write 1 Write 0 Function 7 SYSCR1 Bit symbol (00E1H) Read/Write After reset Function 7 SYSCR2 Bit symbol (00E2H) Read/Write After reset Always Write 0 Function Under ...
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EMCCR0 Bit symbol PROTECT (00E3H) Read/Write R After reset 0 Protect flag Always 0: OFF Write Function EMCCR1 Bit symbol (00E4H) Read/Write After reset Function Under development R/W R/W R ...
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System clock controller The system clock controller generates the system clock signal (f internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<GEAR0 to GEAR2> sets the high-frequency clock gear to either 1, 2, ...
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Prescaler clock controller For the internal I/O (TMRA01 to TMRA45, TMRB0 and SIO0 ) there is a prescaler which can divide the clock. The T clock input to the prescaler is either the clock f divided by 2. The ...
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Under development (2) Protection of register contents (Purpose) An item for mistake-operation by inputted noise. To execute the program certainty which is occurred mistake-operation, the protect-register can be disabled write-operation for the specific SFR. Write-disabled SFRs 1. CS/WAIT controller B0CS, ...
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Standby controller (1) HALT Modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1,HALTM0> register. The subsequent actions performed in each mode are as follows: ...
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Under development (2) How to clear a HALT mode The Halt state can be cleared by a Reset interrupt request. The combination of the value in <IFF0 to IFF2> of the Interrupt Mask Register and the current ...
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Table 3.4.4 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt HALT mode NMI INTWDT INT0 to 4 INT5 INTTA0 to 5 INTTB-00, 01, OF0 INTRX0, TX0 INTRX1, TX1 INTAD RESET : After clearing the HALT ...
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Operation IDLE2 Mode In IDLE2 Mode only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.4.5 illustrates an example of the timing for clearance of the ...
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STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator Pin status in STOP Mode depends on the settings in the SYSCR2<DRVE> register. Table 3.4.6 summarizes the state of these pins in STOP Mode. After ...
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Table 3.4.6 Pin states in STOP Mode Pin Names Input/ Output Mode P10 to 17(D8 to 15) Input Mode Output Mode Input/output Mode P20 to 27(A16 to 23), Input/output Mode Output , Output pin ...
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Interrupts Interrupts are controlled by the CPU Interrupt Mask Register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C829 has a total of 33 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources (Software interrupts,Illegal ...
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Interrupt processing Interrupt apecified by micro DMA start vector? No Interrupt vector calue “V” read Interrupt request F/F clear General-purpose interrupt PUSH PC processing PUSH SR SR<IFF2:0> Level of accepted interrupt INTNEST INTNEST PC (FFFF00H Interrupt processing program RETI instruction ...
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General-purpose interrupt processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the ...
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... Table 3.5.1 TMP91C829F interrupt vectors and micro DMA start vectors Default Interrupt Source or Source of Micro DMA Type Priority Request 1 Reset or [SWI0] instruction 2 [SWI1] instruction 3 Illegal instruction or [SWI2] instruction 4 [SWI3] instruction 5 Non-mask [SWI4] instruction able 6 [SWI5] instruction 7 [SWI6] instruction 8 [SWI7] instruction 9 : NMI pin input ...
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Micro DMA processing In addition to general-purpose interrupt processing, the TMP91C829 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the ...
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This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see (4) “Transfer Mode Register”. As the transfer counter is a 16-bit counter, micro DMA ...
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Soft start function In addition to starting the micro DMA function by interrupts, TMP91C815 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to ...
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Detailed description of the Transfer Mode Register 8 bits DMAM0 Mode DMAM3 Number of Transfer Bytes 000 000 00 Byte transfer (fixed) 01 Word transfer 10 4-byte transfer 001 00 Byte transfer 01 Word transfer ...
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Interrupt controller operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. ...
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Interrupt request F/F NMI S Q RESET R interrupt vector read INTWD Priority setting register CLR Dn 2 Interrupt request F/F INT0 S Q Reset R Interrupt request flag Interrupt vector read Micro DMA acknowledge ...
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Interrupt priority setting registers Name Symbol Address 7 INTE0 & IADC INTE0AD 90h INTAD R Enable 0 INT1 I2C & INTE12 91h INT2 R Enable 0 INT3 I4C & INTE34 92h INT4 R Enable 0 INT5 INTE5 93h Enable ...
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Name Symbol Address 7 Interrupt ITB01C Enable INTETB0 99H R TMRB0 0 Interrupt Enable INTETB0V 9BH TMRB0V (over flow) Interrupt ITX0C Enable INTES0 9CH R Serial 0 0 Interrupt ITX1C Enable INTES1 9DH R Serial 1 0 INTTC0 ITC1C & ...
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External interrupt control Name Symbol Address 7 Interrupt 0 8CH Input Mode IIMC0 (no RMW) Write 0 control 0 INT2 level Enable 0 Edge detect INT 1 Level INT INT1 level Enable 0 Edge detect INT 1 Level INT ...
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Setting functions on External Interrupt pins Interrupt pin NMI INT0 INT1 INT2 INT3 INT4 INT5 (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.5.1, ...
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Micro DMA start vector registers These registers assign micro DMA processing to an sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated ...
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Under development (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the ...
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Port Functions The TMP91C829 features 53 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table ...
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Table 3.6.2 (a) I/O Registers and Their Specifications Port Name Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 2 P20 to P27 Output port A16 to A23 output Port Z PZ2 Input port (without ...
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Table 3.6.2 (b) I/O Registers and Their Specifications Port Name Port 8 P80 P81 P82 P83 P84 P85 P86 P87 Port 9 P90 P93 to P96 P93 P94 P95 P96 Port A PA3 PA0 to PA7 Note 1: When PA1 ...
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After a Reset the port pins listed below function as general-purpose I/O port pins. A Reset sets I/O pins which can be programmed for either input or output to be input port pins. Setting the port pins for internal function ...
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Figure 3.6.1 shows an example external interface circuit when the bus release function is used. When the bus is released, neither the internal memory nor the internal I/O can be accessed. However, the internal I/O continues to operate ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting , the control register P1CR to 0 and sets Port ...
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Port 2 (P20 to P27) Port 8-bit output port. In addition to functioning as a output port, Port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for ...
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Port 5 (P53 to P56) Port 4-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch the control register P5CR and the ...
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Under development Reset Direction control (on bit basis) P5CR Write Function conrtol (on bit basis) P5FC Write Output latch B Output buffer P5 Write BUSAK P5 Read Figure 3.6.7 Port 54 Reset Direction control (on bit basis) ...
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Under development Reset Direction control (on bit basis) P5CR write Function contorl (on bit basis) P5FC write S Output latch P5 write S B selector P5 write A Level or edge INT0 & rising edge or falling edge IIMC0<I0LE, I0EDGE> ...
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Bit symbol P5 Read/Write (000DH) After Reset 7 Bit symbol P5CR Read/Write (0010H) After Reset 7 Bit symbol Read/Write P5FC After Reset (0011H) Function Always 0: PORT Write 0 1: INT0 Note1: Read-modify-write is prohibited for register P5CR, P5FC. ...
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Port 6 (P60 to P63) Port 4-bit output port. When reset, the P62 latch is cleared to 0 while the P60-P63 output latches are set addition to functioning as an output port, ...
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Bit symbol P6 Read/Write (0012H) After Reset 7 Bit symbol P6FC Read/Write (0015H) After Reset Function Note: Read-Modify-Write is prohibited for the registers P6FC. Under development Port 6 Register P63 Port 6 Function Register 6 5 ...
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Port 7 (P70 to P75) Port 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port input port. In addition to functioning as a general-purpose ...
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Reset Direction contorol (on bit basis) P7CR write Function control (on bit basis) P7FC write S A Output latch P7 write B Timer F/F OUT TA1OUT : Timer1 TA5OUT : Timer5 P7 read Figure 3.6.15 Port 71, 74 Reset Direction ...
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Bit symbol P7 Read/Write (0013H) After Reset 7 Bit symbol P7CR Read/Write (0016H) After Reset 7 Bit symbol Read/Write P7FC After Reset (0017H) Function 0: PORT 1: INT2 input Note: Read-Modify-Write is prohibited for the registers P7CR and P7FC. ...
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Port 8 (P80 to P87) Port pins Port pins constitute a 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets P80 to P87 ...
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Under development (2) Port pin 81 (RXD0), 85 (RXD1) Port pin 81, 85 are I/O port pins and can also be used as RXD input pin for the serial channels. Reset Derection control (Each bit can be set individually.) P8CR ...
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Under development (4) Port pin 83 (/STS0), 87 (/STS1) Port pin 83, 87 are I/O port pins and can also be used as STS output pin for the received data request signal. Reset Direction control (on bit basis) P8CR write ...
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Bit symbol P87 P8 Read/Write (0018H) After Reset 1 7 Bit symbol P87C P8CR Read/Write (001AH) After Reset 0 7 Bit symbol P87F Read/Write W P8FC After Reset 0 (001BH) Function 0: PORT 0: PORT 1: STS1 1: SCLK1 ...
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Port 9 (P90, P93 to P96) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output, Resetting sets port9 input port,It also sets all bits in the output ...
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P93 to P96 Reset Direction contorol (on bit basis) P9CR write S Output latch P9 write P9 read TB0IN0 TB0IN1 Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch P9 ...
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Bit symbol P9 Read/Write (0019H) After Reset 7 Bit symbol P9CR Read/Write (001CH) After Reset 7 Bit symbol Read/Write P9FC After Reset (001DH) Function 0: PORT 1: TB0OUT1 Note: Read-Modify-Write is prohibited for the registers P9CR and P9FC. Under ...
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Port A (PA0 to PA7) Port 8-bit input port and can also be used as the analog input pins for the internal AD converter. Port A read AD Read ADTRG (for PA3 only Bit ...
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Port Z (PZ2 PZ3) Port 4-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting resets all bits of the output latch the control register PZCR and the function ...
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Bit symbol PZ Read/Write (007DH) After Reset 7 Bit symbol PZCR Read/Write (007EH) After Reset 7 Bit symbol PZFC Read/Write (007FH) After Reset Function Under development Port Z Register PZ3 W Port Z control register 6 ...
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Chip Select/Wait Controller On the TMP91C829, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). ...
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Memory Start Address Registers Figure 3.7.1 shows the Memory Start Address Registers. The Memory Start Address Registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The eight most significant bits (A23 to ...
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Memory Address Mask Registers Figure 3.7.3 shows the Memory Address Mask Registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). ...
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Setting Memory Start Addresses and Address Areas Figure 3.7.4 shows an exa to ple in which CS0 is specified 64-Kbyte address area starting at 010000H. First, MSAR0<S23 to S16>, the eight most significant bits of the ...
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Address Area Size Specification Table 3.7.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A size in question using the memory start address register and memory ...
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Chip Select/Wait Control Registers Figure 3.7.5 lists the Chip Select/Wait Control Registers. The Master Enable/Disable, Chip Select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 plus any other) are set ...
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Master Enable bits Bit 7 (<B0E>, <B1E>, <B2E> or <B3E> chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables ...
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Wait control Bits (<B0W0 to B0W2>, <B1W0 to B1W2>, <B2W0 to B2W2>, <B3W0 to B3W2> or <BEXW0 to BEXW2> chip select/wait control register specify the number of waits that are to be inserted when ...
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Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: Set the Memory Start Address Registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the ...
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Connecting external memory Figure 3.7.6 shows an example of how to connect external memory to the TMP91C829. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C219 ...
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Timers (TMRA) The TMP91C829 features six built-in 8-bit timers. These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module consists of two channels and can operate in any of the following four operating modes. 8-Bit ...
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Prescaler Prescaler Run/Clear 128 256 512 clock T16 T256 TA01RUN<TA0RUN> Selector External input clock: TA0IN T1 8-bit up counter T4 (UC0) T16 Over flow TA01MOD TA01MOD <PWM01, <TA0CLK1, ...
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Prescaler Prescaler Run/clear 128 clock: T0 256 512 T1 T4 T16 T256 TA23RUN<TA2RUN> Selector T1 8-bit Up-Counter T4 (UC2) T16 Over flow TA23MOD TA23MOD <TA2CLK1, TA2CLK 0> <PWM21, PWM20> Match 8-bit ...
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Prescaler Prescaler Run/Clear 128 256 512 clock T16 T256 TA45RUN<TA4RUN> Selector External input clock: TA4IN T1 8-Bit Up-Counter T4 (UC4) T16 Over flow TA45MOD TA45MOD <PWM41, <TA4CLK1, TA4CLK ...
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Operation of each circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock T0 is divided by 4 and input to this prescaler. T0 can be either f fc/16 and is SYSCR0<PRCK1,PRCK0>. The prescaler’s operation ...
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Under development (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up-counter, the ...
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Under development (4) Comparator (CP0) The comparator compares the value in an up-counter with the value set in a timer register. If they match, the up-counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFRs 7 Bit symbol TA0RDE Read/Write R/W TA01RUN After Reset 0 (0100H) Double buffer Function 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN are undefined ...
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Bit symbol TA4RDE Read/Write R/W TA45RUN After Reset 0 (0110H) Double buffer Function 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA45RUN are undefined when read. ...
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Bit symbol TA01M1 Read/Write After Reset 0 TA01MOD Operation mode (0104H) 00: 8-Bit Timer Mode Function 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode Under development TMRA01 Mode Register TA01M0 PWM01 PWM00 ...
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Bit symbol TA23M1 Read/Write After Reset 0 TA23MOD Operation mode (010CH) 00: 8-Bit Timer Mode Function 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode Under development TMRA23 Mode Register TA23M0 PWM21 PWM20 ...
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Bit symbol TA45M1 Read/Write After Reset 0 TA45MOD Operation mode (0114H) 00: 8-Bit Timer Mode Function 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode Under development TMRA45 Mode Register TA45M0 PWM41 PWM40 ...
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TA1FFCR Bit symbol (0105H) Read/Write After Reset Read-Modif y-Write instructions are Function prohibited. Note: The values of bits TA1FFCR are undefined when read. Under development TMRA1 Flip-Flop Control Register TAFF1C1 00: Invert ...
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TA3FFCR Bit symbol (010DH) Read/Write After Reset Read-Modif y-Write instructions are Function prohibited. Note: The values of bits TA3FFCR are undefined when read. Under development TMRA3 Flip-Flop Control Register TAFF3C1 00: Invert ...
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TA5FFCR Bit symbol (0115H) Read/Write After Reset Read-Modif y-Write instructions are Function prohibited. Note: The values of bits TA5FFCR are undefined when read. Under development TMRA5 Flip-Flop Control Register TAFF5C1 00: Invert ...
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Operation in each mode (1) 8-Bit Timer Mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop ...
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Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.32 s square wave pulse from ...
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Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-Bit Timer Mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up-counter 1 (when TA0REG 5) ...
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The comparator match signal is output from TMRA0 each time the up-counter UC0 matches TA0REG, where the up-counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse ...
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In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up-counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller ...
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Example: To generate 1/4-duty 113.636kHz pulses (at fc 8.8 s Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: f Calculate the value which should be set in the timer register. To obtain a frequency of ...
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PWM Output Mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT ...
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In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match ...
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Select Prescaler Gear Value Clock <GEAR2 to GEAR0> <PRCK1 to PRCK0> 000 (fc) 001 (fc/ (fc/ FPH 011 (fc/8) 00 (fc/16) 10 XXX (fc/16 clcok) XXX: Don’t care (5) Settings for each mode Table 3.8.4 shows ...
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Timer/Event Counters (TMRB) The TMP91C829 incorporates multifunctional 16-bit timer/event counter (TMRB0) which has the following operation modes: 16-Bit Interval Timer Mode 16-Bit Event Counter Mode 16-Bit Programmable Pulse Generation (PPG) Mode The timer/event counter channel consists of a ...
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Run/ Clear TB0RUN Prescaler clock: T0 <TB0PRUN> T16 TB0MOD <TB0CP0> TA1OUT Capture, from TMRA01) ( External INT TB0IN0 input control TB0IN1 Slelector TB0MOD T1 <TB0CPM1 to T4 TB0CPM0> T16 TB0MOD<TB0CLK1 to TB0CLK0> 16-Bit ...
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Operation of each block (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock ( T0) is divided clock (divided by 4) from selected clock by the register SYSCR0<PRCK1 to PRCK0> of clock-gear. This prescaler ...
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Under development (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up-counter UC0 matches the value set in this timer register, the Comparator Match Detect signal will ...
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Under development (5) Capture input control This circuit controls the timing to latch the value of up-counter UC0 into TB0CP0, TB0CP1. The latch timing TB0MOD<TB0CPM1, TB0CPM0>. In addition, the value in the up-counter can be loaded into a capture register ...
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SFR 7 TB0RUN Bit symbol TB0RDE (0180H) Read/Write R/W After Reset 0 Function Double Write 0 Buffer 0: Disable 1: Enable Note: The 1, 4 and 5 of TB0RUN are read as undefined value. Under development TMRB0 Run ...
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TB0MOD Bit symbol TB0CT1 (0182H) Read/Write R/W After Reset 0 Function TB0FF1 inversion 0: Disable trigger 1: Enable trigger Invert when Invert when the UC the UC value is value captured to matches the TB0CP1. value in TB0RG1. Under ...
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TB0FFCR Bit symbol TB0FF1C1 TB0FF1C0 (0183H) Read/Write W* After Reset 0 Function Control TB0FF1 00: Invert 01: Set 10: Clear 11: Don’t care Always read as 11 Under development TMRB0 Flip-Flop Control Register TB0C1T1 TB0C0T1 TB0E1T1 ...
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Operation in each mode (1) 16-Bit Interval Timer Mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1. ...
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Under development (3) 16-Bit Programmable Pulse Generation (PPG) Output Mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either Low-active or High-active. The PPG mode is obtained by inversion of the ...
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The following block diagram illustrates this mode. Selector TB0IN0 T1 T4 T16 Selector TB0RG0-WR TB0RUN<TB0RDE> Figure 3.9.7 Block Diagram of 16-BIT Mode The following example shows how to set 16-Bit PPG Output Mode TB0RUN ...
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Serial Channel TMP91C829 includes one serial I/O channel. Either UART Mode (asynchronous transmission) or I/O Interface Mode (synchronous transmission) can be selected. I/O Interface Mode UART Mode In Mode 1 and Mode 2 a parity bit can be added. ...
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Block diagrams Figure 3.10 block diagram representing Serial Channel 0. prescaler T32 Serial clock generation circuit BR0CR <BR0CK1, 0> BR0CR <BR0S3 to 0> T32 BR0CR ...
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T32 Serial clock generation circuit BR1CR <BR0CK1, 0> BR1CR <BR1S3 to 0> T32 BR1CR <BR1ADDE> Baud rate generator f SYS SCLK1 shared with P86 I/O Interface Mode ...
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Operation of each circuit (1) Prescaler, Prescaler clock select There is a 6-bit prescaler for waking serial clock. The clock selected using SYSCR<PRCK1:PRCK0> is divided by 4 and input to the prescaler as T0. The prescaler can be run ...
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Under development (2) Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, T0, T2 ...
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Under development • (16-K)/16 divider (UART Mode only) Accordingly, when the source clock frequency (fc) = 4.8 MHz, the input clock frequency = T0 , the frequency divider N (BR0CR<BR0S3 to BR0S0> (BR0ADD<BR0K3 to BR0K0>) ...
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Table 3.10.3 Transfer rate selection (when baud rate generator Is used and BR0CR <BR0ADDE> fc [MHz] Frequency Divider 9.830400 12.288000 14.745600 Note 1: Transfer rates in I/O Interface Mode are eight times faster than the values given above. Note 2: ...
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Under development (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> the basic clock is generated by dividing the ...
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Under development (6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or ...
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Handshake function Serial Channels 0 and 1 each have a sent in units of one frame; thus, Overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD <CTSE> setting. When the CTS0 transmission is halted ...
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Under development (9) Transmission Buffer The Transmission Buffer (SC0BUF) shifts out and sends the transmission data written from the CPU, in order one bit at a time starting with the least significant bit (LSB) and finishing with the most significant ...
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Under development (12) Timing generation In UART Mode Receiving Mode (Note) Interrupt timing Center of last bit (bit 8) Framing error timing Center of stop bit Parity error timing Overrun error timing Center of last bit (bit 8) Note: In ...
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SFR 7 SC0MOD0 Bit symbol TB8 (0202H) Read/Write After Reset 0 Transfer Hand shake data bit 8 0: CTS 1: CTS Function Figure 3.10.7 Serial Mode Control Register (channel 0, SC0MOD0) Under development CTSE RXE WU ...
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SC1MOD0 Bit symbol TB8 (0209H) Read/Write After Reset 0 Transfer Hand shake data bit 8 0: CTS 1: CTS Function Figure 3.10.8 Serial Mode Control Register (channel 1, SC1MOD0) Under development CTSE RXE WU R/W 0 ...
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SC0CR RB8 Bit symbol (0201H) Read/Write R After Reset 0 Received Parity data bit 8 0: odd 1: even Function Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing ...
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SC1CR RB8 Bit symbol (0208H) Read/Write R After Reset 0 Received Parity data bit 8 0: odd 1: even Function Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing ...
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BROCR Bit symbol BR0ADDE (0203H) Read/Write After Reset 0 Received (16 K)/16 data Bit 8 division Function 0: Disable 1: Enable (16 K)/16 division enable 0 Disable 1 Enable 7 BR0ADD Bit symbol (0204H) Read/Write After Reset Function Sets ...
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BR1CR Bit symbol BR1ADDE (020AH) Read/Write After Reset 0 Received (16 K)/16 data Bit 8 division Function 0: Disable 1: Enable (16 K)/16 division enable 0 Disable 1 Enable 7 BR1ADD Bit symbol (020BH) Read/Write After Reset Function Sets ...
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TB7 SC0BUF (0200H) 7 RB7 Note: Prohibit Read modify write for SC0BUF. Figure 3.10.13 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF) 7 SC0MOD1 Bit symbol I2S0 (0205H) Read/Write R/W After Reset 0 IDLE2 Function 0: Stop 1: Run Figure ...
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Operation in each mode (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK Output Mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer. When all the data has been output, INTES0 <ITX0C> ...
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Receiving In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag INTES0<IRX0C> is cleared as the received data is read. ...
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Under development Transmission and Receiving (Full Duplex Mode) When Full Duplex Mode is used, set the Receive Interrupt Level to 0 and set enable the level of transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving ...
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Under development This UPU have STS0, STS1 pins that request the next data send to the CPU. P8CR sets to output mode, P8FC sets STS using mode, and bit 0 of SC0MOD1 (SC1MOD1) register sets H revel. And then STS ...
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Under development (2) Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting the Serial Channel Mode Register SC0MOD0<SM1,SM0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled ...
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Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Main settings P8CR SC0MOD SC0CR ...
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Protocol Select 9-Bit UART Mode on the master and slave controllers. Set the SC0MOD0<WU> bit on each slave controller enable data receiving. The master controller transmits data one frame at a time. Each frame includes an 8-bit ...
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Under development Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. SYS TXD RXD TXD Master Slave 1 Select code 00000001 Since Serial Channels 0 and 1 operate ...
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Analog/Digital Converter The TMP91C829 incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11 block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are shared with the ...
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Analog/Digital converter registers The AD converter is controlled by the two AD Mode Control Registers: ADMOD0 and ADMOD1. The eight AD Conversion Data Upper and Lower Registers (ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L) store the results of AD conversion. Figure ...
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ADMOD1 Bit symbol VREFON (02B1H) Read/Write R/W After Reset 0 VREF IDLE2 application 0: Stop Function control 1: Operate 0: OFF 1: ON Figure 3.11.3 AD Converter Related Register Under development AD Mode Control Register ...
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ADREG04L Bit symbol ADR01 (02A0H) Read/Write R After Reset Undefined Stores lower 2 bits of AD conversion result Function 7 ADREG04H Bit symbol ADR09 (02A1H) Read/Write After Reset Function 7 ADREG15L Bit symbol ADR11 (02A2H) Read/Write R After Reset ...
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ADREG26L Bit symbol ADR21 (02A4H) Read/Write R After Reset Undefined Stores lower 2 bits of AD conversion result. Function 7 ADREG26H Bit symbol ADR29 (02A5H) Read/Write After Reset Function 7 ADREG37H Bit symbol ADR31 (02A6H) Read/Write R After Reset ...
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Description of operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between ...
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Under development (4) AD conversion modes and the AD Conversion End interrupt The four AD conversion modes are: Channel Fixed Single Conversion Mode Channel Scan Single Conversion Mode Chanel Fixed Repeat Conversion Mode Channel Scan Repeat Conversion Mode The ADMOD0<REPET> ...
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Channel Scan Repeat Conversion Mode Setting ADMOD0<REPET> and ADMOD0<SCAN> selects Conversion Channel Scan Repeat Conversion Mode. In this mode data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0<EOCF> is set ...
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Table 3.11.3 Correspondence Between Analog Input Channels and AD Conversion Result Registers Analog input channel (Port A) AN0 AN4 AN1 AN5 AN2 AN6 AN3 AN7 <ADRxRF>, bit 0 of the AD conversion data lower register, is used as the AD ...
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Watchdog timer (runaway detection timer) The TMP91C829 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to Normal state when it detects that the CPU has started to malfunction (runaway) due ...
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The watchdog timer consists of a 22-stage binary counter which uses the system clock ( the input clock. The binary counter can output f SYS Selecting one of the outputs using WDMOD<WDTP1,WDTP0> generates a 21 ...
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Control registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog Timer Mode Register (WDMOD) Setting the detection time for the watchdog timer in <WDTP> This 2-bit register is used for setting the ...
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WDMOD Bit symbol WDTE (0300H) Read/Write R/W After Reset 1 WDT control Select detecting time 1: enable 00: 2 01: 2 Function 10: 829/f 11: 2 Watchdog timer detection time SYSCR1 Gear Value <GEAR2 to GEAR0> 000 (fc) 001 ...
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Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1,WDTP0> has elapsed. The watchdog timer must be zero-cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if ...
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Multi-Vector Control 3.13.1 Multi-Vector Controller (1) Outline By rewriting the value of multi-vector control resister (MVEC 0 and 1), a vector table is arbitrarily movable. (2) Control resister The amount of 228 bytes become an interruption vector area from ...
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Multi-Boot Mode (1) Outline The TMP91C829 has multi-boot mode available as an on-board programming operation mode. When in multi-boot mode, the boot ROM is mapped into memory space. This boot ROM is a mask ROM that contains a program ...
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Under development (3) Memory Map Figure 3.12.2 shows memory maps for multi-chip and multi-boot modes. When start up in multi-boot mode, internal boot ROM is mapped in FFF800H address, the boot program starts up. When start up in multi-chip mode, ...
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SIO interface specifications The following shows the SIO communication format in multi-boot mode. Before on-board programming can be executed, the communication format on the programming controller side must also be set up in the same way as for the ...
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Table 3.13.3 Baud Rate Modification Command Baud Rate (bps) 9600 Modification command 28H Table 3.13.4 Operation Command Operation command C0H Table 3.13.5 Version Management Information Version Information FRM1 Table 3.13.6 Frequency Measurement Result Data Frequency of Resonator 16.000 (MHz) 1000H ...
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Under development 6. The 7th byte is used to send information of the measured frequency. The controller should check that the frequency of the resonator is measured correctly. 7. The receive data in the 8th byte is the baud rate ...
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Under development (ii) Error Code The boot program sends the processing status to the controller using various code. The error code is listed in the table below. Table 3.13.7 Error Code Error Code 62H Baud rate modification error occurred. 64H ...
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Transmit a user program not by the ASCII code but by binary. However, start mark “:” is 3AH (ASCII code). Example: Transmit data in the case of writing in 16 bytes data from address 1060H Data Record 3A 10 ...
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Ports setup of the boot program Only ports shown in Table 3.13.9 are set up in the boot program. At the time of boot program use, be careful of the influence on a user system. Do not use P60 ...
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Electrical Characteristics (tentative) 4.1 Absolute Maximum Ratings Parameter Power Supply Voltage (5 V) Power Supply Voltage (3 V) Input Voltage Output Current (per pin) Output Current (per pin) Output Current (total) Output Current (total) Power Dissipation (Ta Soldering Temperature ...
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DC Characteristics (2/2) Parameter Symbol Input Leakage Current ILI Output Leakage Current ILO Power Down Voltage VSTOP (@STOP, RAM back-up) Pull-up Resistor RESET RRST Pin Capacitance CIO Schmitt Width VTH , , INT0 RESET NMI Programmable RKH Pull-up Resistor NORMAL ...
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AC Characteristics (1) HVcc 5.0 V 5%, LVcc No. Parameter 1 f Period ( x ) FPH Vaild / Fall Rise A0 to A23 Hold Rise A0 to A23 Hold ...
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Read Cycle t FPH f FPH CSn WAIT Port Input Under development APH t APH2 91C829-166 TMP91C829 t CAR ...
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Write Cycle f FPH CSn WAIT Port Output , WR WAIT Under development t APO 91C829-167 TMP91C829 t CAW t WD 2001-02-15 ...
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AD Conversion Characteristics parameter Analog Reference Voltage ( ) Analog Reference Voltage ( ) Analog Input Voltage Range Analog Current for Analog Reference Voltage <VREFON> 1 <VREFON> 0 Error (not including quantizing errors) Note 1: 1 LSB (VREFH Note ...
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Serial Channel Timing (I/O Internal Mode) Note: Symbol “x” in the above table means the period of clock “f “f ” for CPU core. The period of f SYS (1) SCLK Input Mode Parameter SCLK Period Output Data SCLK ...
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Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1) Parameter Clock Perild Clock Low Level Width Clock High Level Width Note: Symbol “x” in the above table means the period of clock “f “f ” for CPU core. The period ...
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Bus Request/Bus Acknowledge BUSRQ BUSAK D0 to D15 A0 to A23 CS0 CS3 HWR Parameter Output Buffer to Low BUSAK High to output Buffer On BUSAK Note 1: Even if the BUSRQ The bus ...
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Table of SFRs (SFR; special function register) The SFRs include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 000FFFH. (1) I/O Port (2) I/O Port Control (3) Interrupt Control (4) Chip ...
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Address Name 0000H P1CR P2FC Address Name 0070H ...
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CS/WAIT Address Name 00C0H B0CS 1H B1CS 2H B2CS 3H B3CS BEXCS 8H MSAR0 9H MAMR0 AH MSAR1 BH MAMR1 CH MSAR2 DH MAMR2 EH MSAR3 FH MAMR3 [5] TMRA Address Name 0100H TA01RUN 1H ...
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TMRB Address Name 0180H TB0RUN 1H 2H TB0MOD 3H TB0FFCR TB0RG0L 9H TB0RG0H AH TB0RG1L BH TB0RG1H CH TB0CP0L DH TB0CP0H EH TB0CP1L FH TB0CP1H [8] 10-bit ADC Address Name 02A0H ADREG04L 1H ADREG04H ...
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I/O port Symbol Name Address 7 P17 P1 PORT1 01H 0 P27 P2 PORT2 06H 1 P5 PORT5 0DH P6 PORT6 12H P7 PORT7 13H P87 P8 PORT8 18H 1 P9 PORT9 19H PA7 PA PORTA 1EH PZ PORTZ ...
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I/O port control (1/2) Symbol Name Address 7 P17C P1CR PORT1 04H Control (Prohibit 0 RMW) P27F P2FC PORT2 09H 1 Function (Prohibit RMW) P5CR PORT5 10H Control (Prohibit RMW) P5FC PORT5 11H Function (Prohibit RMW) P6FC PORT6 15H ...
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I/O Port control (2/2) Symbol Name Address 7 P9CR PORT9 1CH Control (Prohibit RMW) P9FC PORT9 1DH (Prohibit Function RMW) PZCR PORT5 7EH Control (Prohibit RMW) PZFC PORT5 7FH Function (Prohibit RMW) ODE Sirial Open 2FH Drain (Prohibit RMW) Under ...
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Interrupt control (1/3) Symbol Name Address 7 Interrupt INTE0AD IADC 90H Enable R 0 & INTAD Interrupt INTE12 I2C 91H Enable R 2 INT2 Interrupt I4C INTE34 92H Enable R 4 INT4 ...
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Interrupt control (2/3) Symbol Name Address 7 Interrupt ITX0C INTES0 9CH Enable R Serial INTTX0 Interrupt ITC1C INTETC-01 A0H Enable R TC0/1 0 Interrupt ITC3C INTETC-23 A1H Enable R TC2/3 0 Under development INTTX0 ...
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Interrupt control (3/3) Symbol Name Address 7 DMA 0 Request DMA0V 80H Vector DMA 1 Request DMA1V 81H Vector DMA 2 Request DMA2V 82H Vector DMA 3 Request DMA3V 83H Vector Interrupt 88H Clear INTCLR (Prohibit Control RMW) DMA Software ...
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Chip select / Wait control (1/2) Symbol Name Address 7 B0E W Block 0 B0CS C0H 0 CS/WAIT 0: DIS control 1: EN Register (Prohibit RMW) B1E W B1CS Block 1 C1H 0 CS/WAIT 0: DIS control 1: EN ...
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Chip select /Wait control (2/2) Symbol Name Address 7 Memory S23 Start MSAR2 CCH Address 1 Reg2 V22 Memory MAMR2 Address CDH 1 Mask Reg2 Memory S23 Start MSAR3 CEH Address 1 Reg3 V22 Memory MAMR3 Address CFH 1 Mask ...
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Clock Gear Symbol Name Address 7 SYSCR0 System E0H Clock 1 Control Always Register 0 Write 1 SYSCR1 System E1H Clock Control Register 1 SYSCR2 System E2H Clock Control Register 2 PROTECT EMCCR0 EMC E3H R Control 0 Register ...
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Timer (1/ TMRA01 Symbol Name Address 7 TA0RDE R/W TA01 Timer 100H 0 RUN RUN Double Buffer 0: Disable 1: Enable 8-Bit 102H TA0REG Timer (Prohibit Register 0 RMW) 8-Bit 103H TA1REG Timer (Prohibit Register 1 ...
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Timer (2/2) (6-3) TMRA45 Symbol Name Address 7 TA4RDE R/W TA45- Timer 0 RUN RUN 110H Double Buffer 0: Disable 1: Enable 8-Bit 112H TA4REG Timer (Prohibit Register 0 RMW) 8-Bit 113H TA5REG Timer (Prohibit Register 1 RMW) TA45M1 ...
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Timer (1/2) (7-1) TMRB0 Symbol Name Address 7 TB0RDE TB0RUN Timer 180H R/W Control 0 Double Buffer 0: Disable 1: Enable TB0CT1 TB0-MOD 16-Bit 182H Timer 0 Source TB0FF1 INV TRG CLK & MODE 0: TRG Disable 1: ...
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UART/Serial Channel (8-1) UART/SIO Channel 0 Symbol Name Address 7 Serial RB7/TB7 SC0BUF Channel 0 200H Buffer RB8 R Serial 0 SC0CR Channel 0 201H Receiving Control data bit 8 TB8 Serial 0 SC0- Channel 0 202H Transmissi MOD0 ...
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UART/SIO Channel 1 Symbol Name Address 7 Serial RB7/TB7 SC1BUF Channel 1 208H Buffer RB8 R Serial 0 SC1CR Channel 1 209H Receiving Control data bit 8 TB8 Serial 0 SC1- Channel 1 20AH Transmissi MOD0 Mode0 on data ...
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AD Converter Symbol Name Address 7 AD EOCF ADMOD 0 MODE 2B0H Reg0 0 1: End AD VREFON ADMOD 1 MODE 2B1H R/W Reg1 0 1: VREF On IDLE2 AD ADM27 ADMOD 2 MODE 2B2H Reg2 0 AD ADM37 ...
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Watchdog Timer Symbol Name Address 7 WDTE WDT R/W WDMOD MODE 300H 1 Reg 1: WDT Enable WDCR WD 301H Control (11) Multi Vector Controllor Symbol Name Address 7 VEC7 MULI R/W MVEC0 VECTA 00AEH 1 Control Symbol Name ...
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Port Section Equivalent Circuit Diagrams • Reading the Circuit Diagrams The gate symbols used are essentially the same as those used for the standard CMOS logic IC [74HCXX] Series. The dedicated signal is described below. STOP: This signal becomes ...
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P53 to P55, P80 to P87, PZ2, PZ3 Output data Output Enable STOP Input data Input Enable ■ PA (AN0 to AN7) Analog input channel select Analog Input Input data ■ P56 (INT0), P70(INT1), P72(INT2),P73(INT3),P75(INT4),P90(INT5) Output data Output Enable ...
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P80 (TXD0) Output data Open-Drain Output Enable STOP Input data ■ NMI NMI Under development Vcc Input Enable Schmitt trigger 91C829-194 TMP91C829 I/O Input 2001-02-15 ...
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AM0 to AM1 Input data ■ RESET Reset WDTOUT Reset Enable ■ X1 and X2 High-Frequency Oscillation Enable ■ VREFH and VREFL VREFON Under development Input Vcc P-ch Schmitt trigger Oscillator P-ch N-ch Clock P-ch VREFH String resistance VREFL ...
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Points to Note and Restrictions (1) Notation a) The notation for built-in / I/O registers is as follows register symbol <bit symbol> e.g.) TA01RUN <TA0RUN> denotes bit TA0RUN of register TA01RUN. b) Read-modify-write instructions An instruction in which the ...
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Points to note a) AM0 and AM1 pins Fix these pins EMU0and EMU1 Open pins. c) Reserved address areas The TMP91C829 noes not have any reserved areas. d) Halt mode (IDLE1) When IDLE1 Mode is used ...