DSP56001FE20 Motorola, DSP56001FE20 Datasheet

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DSP56001FE20

Manufacturer Part Number
DSP56001FE20
Description
24-bit general purpose digital signal processor, 20.5MHz
Manufacturer
Motorola
Datasheet

Specifications of DSP56001FE20

Case
QFP
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
SYMPHONY ™ AUDIO DSP FAMILY
24-BIT DIGITAL SIGNAL PROCESSORS
Motorola designed the Symphony™ family of high-performance, programmable Digital Signal
Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic,
ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by
Motorola for integration into products like audio/video receivers, televisions, and automotive
sound systems with such user-developed features as digital equalization and sound field
processing. The DSP56004 is an MPU-style general purpose DSP, composed of an efficient 24-bit
Digital Signal Processor core, program and data memories, various peripherals optimized for
audio, and support circuitry. As illustrated in Figure 1 , the DSP56000 core family compatible
DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial
Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated
I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE ) port.
©1996, 1997 MOTOROLA, INC.
PLL
OnCE
DSP56000
24-Bit
Core
Clock
Gen.
3
TM
Internal
Switch
Port
Data
Bus
Purpose
General
Output
4
Input/
IRQA
Freescale Semiconductor, Inc.
Interrupt
Control
4
For More Information On This Product,
,
4
Interface
IRQB, NMI
Serial
Audio
(SAI)
Program Control Unit
Figure 1 DSP56004 Block Diagram
Generation
Address
Go to: www.freescale.com
9
Unit
Controller
Program
Decode
,
Interface
RESET
Serial
(SHI)
Host
GDB
PDB
XDB
YDB
5
Interface
Generator
External
Memory
Program
Address
(EMI)
29
PAB
XAB
YAB
*Refer to Table 1 for memory configurations.
Memory*
Program
DSP56004ROM
24
Two 56-Bit Accumulators
24 + 56
Memory*
X Data
Data ALU
DSP56004
Order this document by:
16-Bit Bus
24-Bit Bus
56-bit MAC
DSP56004/D, Rev. 3
Memory*
Y Data
AA0248

Related parts for DSP56001FE20

DSP56001FE20 Summary of contents

Page 1

... Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by Motorola for integration into products like audio/video receivers, televisions, and automotive sound systems with such user-developed features as digital equalization and sound field processing ...

Page 2

... PIN PIN PIN PIN Note: Values for and For More Information On This Product, TABLE OF CONTENTS 1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications. OH DSP56004/D, Rev to: www.freescale.com Voltage MOTOROLA ...

Page 3

... Table 1 Memory Configuration (Word width is 24 bits) Part Type ROM 1 DSP56004 None 2 DSP56004ROM 2560 Note data ROM is programmed with 2. These ROMs may be factory programmed with data/program provided by the application developer. MOTOROLA For More Information On This Product, Program X Data RAM ROM RAM 512 256 256 256 256 256 x ...

Page 4

... Quad Flat Pack surface-mount package 2.20 mm (2.15–2.45 mm range); 0.65 mm lead pitch • Complete pinout compatibility between DSP56004, DSP56004ROM, DSP56007, and DSP56009 for easy upgrades • power supply iv For More Information On This Product Sony, and Matsushita audio DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 5

... Table 2 lists the documents that provide a complete description of the DSP56004 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 2 DSP56004 Documentation ...

Page 6

... Freescale Semiconductor, Inc. DSP56004 Product Documentation vi For More Information On This Product, DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 7

... CC Ground (GND) Phase Lock Loop (PLL) External Memory Interface (EMI) Interrupt and Mode Control Serial Host Interface (SHI) Serial Audio Interface (SAI) General Purpose Input/Output (GPIO) On-Chip Emulation (OnCE) port Total MOTOROLA For More Information On This Product, SECTION 1 Number of Signals ...

Page 8

... Rec0 Rec1 Tran0 Tran1 Tran2 Port A External Memory Interface GPIO Mode/Interrupt OnCE™ Control Port Reset 80 signals DSP56004/D, Rev to: www.freescale.com MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ WSR SCKR SDI0 SDI1 WST SCKT SDO0 SDO1 SDO2 4 GPIO0–GPIO3 DSCK/OS1 DSI/OS0 DSO DR AA0249G MOTOROLA ...

Page 9

... Serial Interface Ground—GND S connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. MOTOROLA For More Information On This Product, Table 1-2 Power Inputs Description provides isolated power for the Phase Lock Loop (PLL). The CCP power rail ...

Page 10

... PLL voltage controlled oscillator output. When the bit is cleared, the PLL is disabled and the DSP’s internal clocks are derived from the clock connected to the EXTAL signal. After hardware RESET is deasserted, the PINIT signal is ignored. DSP56004/D, Rev to: www.freescale.com . The required capacitor or GND. MOTOROLA ...

Page 11

... Table 1-6 MWR Output Table 1-6 MRD Output MOTOROLA For More Information On This Product, Signal Description Memory Address Lines 0–14—The MA0–MA10 lines provide the multiplexed row/column addresses for DRAM accesses. Lines MA0–MA14 provide the non-multiplexed address lines 0–14 for SRAM accesses. ...

Page 12

... Driven High Driven High Driven High Driven High Driven Low Driven High Previous State Previous State Driven High Driven High Driven High Driven High Driven Low Driven High Driven High Driven High Driven High Driven High Driven High Driven High MOTOROLA ...

Page 13

... Signal Name Type Reset MODA Input Input (MODA) Mode Select A—This input signal has three functions: IRQA MOTOROLA For More Information On This Product, Signal Description • to work with the MODB and MODC signals to select the DSP’s initial operating mode, • ...

Page 14

... However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to function as MODB. DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 15

... Input (MODC) Mode Select C—This input signal has two functions: edge- triggered NMI RESET input active MOTOROLA For More Information On This Product, Signal Description • to work with the MODA and MODB signals to select the DSP’s initial operating mode, and • ...

Page 16

... Fosc frequency is / for the SPI mode and mode. This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). DSP56004/D, Rev to: www.freescale.com Fosc / for the 6 Fosc / for the 5 MOTOROLA ...

Page 17

... Input or Output MOSI Input or Tri-stated Output HA0 Input MOTOROLA For More Information On This Product, State during Signal Description Reset SPI Master-In-Slave-Out (MISO)—When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data ...

Page 18

... HREQ to proceed to the next transfer. Note: This signal is tri-stated during hardware, software, individual reset, or when the HREQ[1:0] bits (in the HCSR) are cleared (no need for external pull-up in this state). DSP56004/D, Rev to: www.freescale.com Slave mode, the 2 C Master mode MOTOROLA ...

Page 19

... Type SDI0 Input SDI1 Input SCKR Input or Output MOTOROLA For More Information On This Product, Signal Description Reset Tri-stated Serial Data Input 0—While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI0 is the serial data input for receiver 0. ...

Page 20

... WSR is high impedance if all receivers are disabled (individual reset), during hardware reset, during software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary. DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 21

... Tri-stated Output WST Input or Tri-stated Output MOTOROLA For More Information On This Product, Signal Description Serial Data Output 0 (SDO0)—SDO0 is the serial output for transmitter 0. SDO0 is driven high if transmitter 0 is disabled, during individual reset, hardware reset, and software reset, or when the DSP is in the Stop state. ...

Page 22

... OS1 signal. When switching from output to input, the signal is tri-stated. Note: If the OnCE port is in use, an external pull-down resistor should be attached to the DSI/OS0 signal. If the OnCE port is not in use, the resistor is not required. DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 23

... Driven Low OS1 Output DSO Output Driven High MOTOROLA For More Information On This Product, On-Chip Emulation (OnCE Signal Description Debug Serial Clock (DSCK)—The DSCK/OS1 signal, when an input, is the signal through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and out of the OnCE port ...

Page 24

... Debug mode. After receiving the acknowledge pulse, DR must be deasserted before sending the first OnCE port command. For more information, see Methods Of Entering The Debug Mode in the Manual . Note: If the OnCE port is not in use, an external pull-up resistor should be attached to the DR line. DSP56004/D, Rev to: www.freescale.com DSP56000 Family MOTOROLA ...

Page 25

... Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MOTOROLA For More Information On This Product, SECTION 2 CAUTION ) ...

Page 26

... V IN (GND – 0. (GND – 0.25 and GND STG Symbol QFP Value 70 16 3.2 JT DSP56004/D, Rev to: www.freescale.com ) dc Value Unit –0 0.25 –40 to +125 C –40 to +120 C –55 to +125 QFP Value Unit ˚ 45.1 C/W ˚ — C/W ˚ — C/W MOTOROLA ...

Page 27

... OL HREQ Internal Supply Current • Normal mode I CCI • Wait mode I CCW 2 • Stop mode I CCS MOTOROLA For More Information On This Product, 50 MHz 66 MHz Min Typ Max Min Typ Max 4.5 5.0 5.5 4.5 5.0 CC 4.0 — V 4.0 — CC 2.5 — ...

Page 28

... V for all pins, except EXTAL, RESET, IH reference levels set at 0.8 V and 2.0 V, respectively. DSP56004/D, Rev. 3 For More Information On This Product, Go to: www.freescale.com 81 MHz Unit Min Typ Max 1.5 — 1.2 2.0 mA — — 10 — pF Section 4 . Actual maximums are IL MOTOROLA ...

Page 29

... PLL enabled (42.5%–57.5% duty cycle) 2 External Clock Input Low—EXTAL Pin • with PLL disabled (46.7%–53.3% duty cycle) • with PLL enabled (42.5%–57.5% duty cycle) MOTOROLA For More Information On This Product substitute with the numbers in Table 2- ...

Page 30

... Min Max Min 15.15 20 409600 15.15 409600 CYC 40 30.3 40 819200 30.3 819200 Expression Min PCAP @ > DSP56004/D, Rev to: www.freescale.com 66 MHz 81 MHz Unit Max Min Max 12.3 ns 12.3 409600 ns 24.7 ns 24.7 819200 ns AA0250 Max Unit MHz 340 MF 480 pF 380 MF 970 pF ) for CCP MOTOROLA ...

Page 31

... When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. RESET MOTOROLA For More Information On This Product, RESET, Stop, Mode Select, and Interrupt Timing Min 25 ...

Page 32

... Figure 2-6 Recovery from Stop State Using IRQA IRQA Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service 2-8 For More Information On This Product IHM V ILM 16 16A 22 General Purpose I/O 27 DSP56004/D, Rev to: www.freescale.com V IHR IRQA IRQB NMI V IL AA0252 AA0253 AA0254 AA0255 AA0256 MOTOROLA ...

Page 33

... RAS or WR Assertion to t CSH t CAS Deassertation CWL 52 RAS Assertion to CAS t RCD Assertion 53 RAS Assertion to t RAD Column Address Valid MOTOROLA For More Information On This Product, External Memory Interface (EMI) DRAM Timing 50 MHz Timing Expression Mode Min Max Min Max Min Max slow fast ...

Page 34

... MOTOROLA ...

Page 35

... WR Assertion to Data Active Assertion to t ROH RAS Deassertation t RWL (Single Cycle Only) Note the number of successive accesses MOTOROLA For More Information On This Product, External Memory Interface (EMI) DRAM Timing 50 MHz Timing Expression Mode Min Max Min Max Min Max slow 9 T – 11 ...

Page 36

... Freescale Semiconductor, Inc. Specifications External Memory Interface (EMI) DRAM Timing 48 MRAS 65 MCAS 55 MA0–MA10 MWR MRD MD0–MD7 Figure 2-8 DRAM Single Read Cycle 2-12 For More Information On This Product Row Address Last Column Address Data In DSP56004/D, Rev to: www.freescale.com AA0257 MOTOROLA ...

Page 37

... Freescale Semiconductor, Inc. 48 MRAS 65 MCAS 55 Row Address MA0–MA10 MWR MRD MD0–MD7 Figure 2-9 DRAM Page Mode Read Cycle MOTOROLA For More Information On This Product, External Memory Interface (EMI) DRAM Timing Col. Address Col. Address Data In Data DSP56004/D, Rev to: www.freescale.com ...

Page 38

... Freescale Semiconductor, Inc. Specifications External Memory Interface (EMI) DRAM Timing 48 MRAS MCAS 55 MA0–MA10 MWR MRD MD0–MD7 Figure 2-10 DRAM Single Write Cycle 2-14 For More Information On This Product Row Address Column Address Data Out DSP56004/D, Rev to: www.freescale.com AA0264 MOTOROLA ...

Page 39

... Freescale Semiconductor, Inc. 48 MRAS 65 MCAS 55 MA0–MA10 Row Address MWR MRD MD0–MD7 Figure 2-11 DRAM Page Mode Write Cycle MOTOROLA For More Information On This Product, External Memory Interface (EMI) DRAM Timing Col. Address Col. Address Data Out Data Out DSP56004/D, Rev to: www ...

Page 40

... MOTOROLA ...

Page 41

... Assertion Assertion Pulse Width Deassertation Assertion Deassertation to Address not Valid 96 Address Valid to Input Data Valid 97 RD Assertion to Input Data Valid MOTOROLA For More Information On This Product, External Memory Interface (EMI) SRAM Timing MHz Symbol Expression Min Max Min Max Min Max ...

Page 42

... H — T – Figure 2-13 SRAM Read Cycle DSP56004/D, Rev to: www.freescale.com 66 MHz 81 MHz Unit — 0 — 0 — ns — 39 — 29.2 — ns — 18 — 11.0 — ns — 2 — 0.2 — — 12 — 10 — 18 — 16.2 ns — 2 — 0.2 — Data In AA0267 MOTOROLA ...

Page 43

... Freescale Semiconductor, Inc. MA0–MA14 MA15/ MCS3 MA16/ / MCS2 MCAS MA17/ / MCS1 MRAS MCS0 WR RD MD0–MD7 MOTOROLA For More Information On This Product, External Memory Interface (EMI) SRAM Timing 100 102 Data Out 104 101 Figure 2-14 SRAM Write Cycle DSP56004/D, Rev to: www.freescale.com ...

Page 44

... MOTOROLA ...

Page 45

... Freescale Semiconductor, Inc. SCKR (RCKP = 1) SCKR (RCKP = 0) SDI0–SDI1 (Data Input) WSR (Input) WSR (Output) Figure 2-15 SAI Receiver Timing MOTOROLA For More Information On This Product, Serial Audio Interface (SAI) Timing 111 112 114 113 111 113 114 112 115 116 ...

Page 46

... SCKT (TCKP = 0) SDO0–SDO2 (Data Output) WST (Input) WST (Output) Figure 2-16 SAI Transmitter Timing 2-22 For More Information On This Product, 111 112 114 113 111 113 114 112 121 124 123 Valid DSP56004/D, Rev to: www.freescale.com 114 114 122 AA0270 MOTOROLA ...

Page 47

... CPHA = 1 slave 143 Serial Clock Low master Period 2 CPHA = 0, CPHA = 1 slave CPHA = 1 slave 144 Serial Clock Rise/Fall master Time slave MOTOROLA For More Information On This Product, Serial Host Interface (SHI) SPI Protocol Timing 0 ILS CC 50 MHz Filter Expression Mode Min Max Min Max Min bypassed — ...

Page 48

... MOTOROLA ...

Page 49

... HREQ In Assertion to master First SCK Edge 162 HREQ In master Deassertation to Last SCK Sampling Edge (HREQ In Set-up Time) CPHA = 1 MOTOROLA For More Information On This Product, Serial Host Interface (SHI) SPI Protocol Timing 50 MHz Filter Expression Mode Min Max Min Max Min bypassed ...

Page 50

... MSB Valid 152 MSB 163 DSP56004/D, Rev. 3 For More Information On This Product, Go to: www.freescale.com 66 MHz 81 MHz Unit Max — 0 — 0 — the user assures that the HTX C ns before C 141 144 141 144 149 LSB Valid 153 LSB AA0271 MOTOROLA ...

Page 51

... SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Figure 2-18 SPI Master Timing (CPHA = 1) MOTOROLA For More Information On This Product, Serial Host Interface (SHI) SPI Protocol Timing 143 144 142 144 148 149 MSB Valid 152 MSB ...

Page 52

... Figure 2-19 SPI Slave Timing (CPHA = 0) 2-28 For More Information On This Product, 143 144 142 144 143 152 153 153 MSB 148 149 MSB Valid DSP56004/D, Rev to: www.freescale.com 141 147 144 160 141 144 151 LSB 149 LSB Valid 159 AA0273 MOTOROLA ...

Page 53

... SCK (CPOL = 1) (Input) 152 150 MISO (Output) MOSI (Input) HREQ (Output) Figure 2-20 SPI Slave Timing (CPHA = 1) MOTOROLA For More Information On This Product, Serial Host Interface (SHI) SPI Protocol Timing 143 144 142 144 143 152 MSB 148 149 MSB ...

Page 54

... Unit Min Max — — — 100 ns t 10.0 — s SCL t 4.7 — s BUF t 4.7 — s SU;STA t 4.0 — s HD;STA t 4.7 — s LOW t 4.0 — s HIGH t — 1 — 0 250 — ns SU;DAT t 0.0 — ns HD;DAT t — 3.4 s VD;DAT t 4.0 — s SU;STO MOTOROLA ...

Page 55

... Conditions to be Considered Master Slave Oper- Oper- Bus Load ating ating Freq. Freq pF, 81 MHz 81 MHz MOTOROLA For More Information On This Product, Serial Host Interface (SHI specified by the value of the HDM5– CCP is: CCP Tc 2 HDM[5: HRS – (HDM5–HDM0 = 2, HRS = 1) (HDM5– ...

Page 56

... MOTOROLA ...

Page 57

... SCL High Period t master HIGH slave 177 SCL Rise Time Output Input 178 SCL Fall Time Output Input 179 Data Set-up Time t SU;DAT MOTOROLA For More Information On This Product, Serial Host Interface (SHI Protocol Timing (Continued) 2 Improved pF Filter Expression Mode bypassed 0 – 2 ...

Page 58

... MOTOROLA i t ...

Page 59

... CCP C Filter mode. DSP56004 User’s Manual 5. Refer to the 173 SCL 177 172 SDA Stop Start 174 188 HREQ MOTOROLA For More Information On This Product, Serial Host Interface (SHI Protocol Timing (Continued) 2 Improved pF Filter Expression Mode 0 for a detailed description of how to use the filtering modes. ...

Page 60

... Valid when the ratio between EXTAL frequency and internal clock frequency equals 1 2-36 For More Information On This Product, Table 2-16 GPIO Timing Expression 204 Valid Figure 2-22 GPIO Timing DSP56004/D, Rev to: www.freescale.com All frequencies Unit Min Max — — — — ns 201 202 AA0276 MOTOROLA ...

Page 61

... Last DSCK Low to DSO Invalid (Hold) 246 DR Assertion to EXTAL Transition #2 for Wake Up from Wait State 247 EXTAL Transition #2 to DSO After Wake Up from Wait State MOTOROLA For More Information On This Product, On-Chip Emulation (OnCE ) Timing Table 2-17 OnCE Timing Min 40 40 ...

Page 62

... Figure 2-23 DSP56004 OnCE Serial Clock Timing 2-38 For More Information On This Product, All frequencies Min 65549 65553 246 230 231 232 DSP56004/D, Rev to: www.freescale.com Unit Max 12 T – — ns — ns 65548 — — ns — ns — — ns — ns 246 AA0277 MOTOROLA ...

Page 63

... OS1 (Output) 241 DSO (Output) OS0 (Output) 241 Note: 1. High Impedance, external pull-down resistor Figure 2-27 DSP56004 OnCE Data I/O Status Timing MOTOROLA For More Information On This Product, On-Chip Emulation (OnCE ) Timing 233 240 ACK (Last) 237 (Last) 235 245 239 ...

Page 64

... Figure 2-30 Synchronous Recovery from Wait State DR (Input) DSO (Output) Figure 2-31 Asynchronous Recovery from Wait State 2-40 For More Information On This Product, 242 244 T0, T2 T1, T3 248 246 247 248 249 DSP56004/D, Rev to: www.freescale.com 243 AA0282 (Next Command) AA0283 AA0284 AA0285 MOTOROLA ...

Page 65

... Freescale Semiconductor, Inc. DR (Input) DSO (Output) Figure 2-32 Asynchronous Recovery from Stop State MOTOROLA For More Information On This Product, On-Chip Emulation (OnCE ) Timing 250 251 DSP56004/D, Rev to: www.freescale.com Specifications AA0286 2-41 ...

Page 66

... Freescale Semiconductor, Inc. Specifications On-Chip Emulation (OnCE ) Timing 2-42 For More Information On This Product, DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 67

... This section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56004 is available in an 80-pin Plastic Quad Flat Pack (PQFP) package. MOTOROLA For More Information On This Product, SECTION 3 PACKAGING DSP56004/D, Rev ...

Page 68

... For More Information On This Product, (Top View) Orientation Mark Figure 3-1 Top View DSP56004/D, Rev to: www.freescale.com 41 V CCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GND S V CCP PCAP GND P PINIT GND Q V CCQ EXTAL SCK/SCL MA0 MA1 MA2 MA3 21 GND A MOTOROLA ...

Page 69

... MA3 21 GND A Note: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration. MOTOROLA For More Information On This Product, (Bottom View) Orientation Mark Figure 3-2 Bottom View DSP56004/D, Rev to: www.freescale.com ...

Page 70

... WST 77 51 SCKR 78 52 GND CCQ 54 GND S DSP56004/D, Rev to: www.freescale.com Pin # Signal Name WSR SDI1 SDI0 DSO DSI/OS0 DSCK/OS1 DR MD7 MD6 MD5 MD4 GND D MD3 MD2 MD1 V CCD MD0 GND D GPIO3 GPIO2 GPIO1 GPIO0 MRD MWR MA17/MCS1/ MRAS MA16/MCS2/ MCAS MOTOROLA ...

Page 71

... S GND 54 S GPIO0 76 GPIO1 75 GPIO2 74 GPIO3 73 HA0 41 HA2 42 HREQ 43 IRQA 37 IRQB 38 MA0 25 MA1 24 MA2 23 MA3 22 MA4 20 MOTOROLA For More Information On This Product, Signal Name Pin # MA5 19 MA6 18 MA7 16 MA8 14 MA9 13 MA10 12 MA11 11 MA12 7 MA13 5 MA14 4 MA15 3 MA16 80 MA17 79 MCAS 80 MCS0 ...

Page 72

... Table 3-3 DSP56004 Power Supply Pins Pin # Signal Name 6 V CCA 17 1 GND CCD 66 GND CCQ GND CCP 31 GND CCS 48 34 GND 3-6 For More Information On This Product, Circuit Supplied Address Bus Buffers Data Bus Buffers Internal Logic PLL Serial Ports DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 73

... - 0.05 A -C- H SEATING PLANE G DATUM -H- PLANE DETAIL C Figure 3-3 80-pin Plastic Quad Flat Pack (PQFP) Mechanical Information MOTOROLA For More Information On This Product - DETAIL A A DETAIL C DATUM -H- PLANE 0. NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. ...

Page 74

... Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56004 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: • The receiving facsimile telephone number including area code or country code • ...

Page 75

... For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the Printed Circuit Board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. MOTOROLA For More Information On This Product, SECTION 4 ...

Page 76

... For More Information On This Product, do not satisfactorily answer whether the thermal determined by a thermocouple, T – T )/P . This value gives a better DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 77

... Section 1. • Take special care to minimize noise levels on the V • If multiple DSP56004 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. MOTOROLA For More Information On This Product, CAUTION precautions are advised and GND pins are less than 0 ...

Page 78

... Minimize the capacitive load on the pins. • Connect the unused inputs to pull-up or pull-down resistors. • Disable unused peripherals. • Disable unused pin activity. 4-4 For More Information On This Product, – 5 5.5mA max) value reflects the typical possible CCI DSP56004/D, Rev to: www.freescale.com ) value CCItyp MOTOROLA ...

Page 79

... TP1 nop jmp MAIN MOTOROLA For More Information On This Product, Power Consumption Considerations r0,x:(r0)+ l:(r0)+,a x:(r0)+,x0 a,p:(r5) TP1 DSP56004/D, Rev to: www.freescale.com Design Considerations y:(r4)+,y0 4-5 ...

Page 80

... At the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. This is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state. 4-6 For More Information On This Product, DSP56004/D, Rev to: www.freescale.com MOTOROLA ...

Page 81

... Freescale Semiconductor, Inc. ORDERING INFORMATION Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information Supply Part Voltage DSP56004 5 V Quad Flat Pack (QFP) 1 DSP56004ROM 5 V Quad Flat Pack (QFP) Note: 1. For additional information on future part development request specific ROM-based support, call your local Motorola Semiconductor sales office or authorized distributor ...

Page 82

... Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “ ...

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