XPC855TZP50D4 Motorola, XPC855TZP50D4 Datasheet

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Advanced Information MPC860EC/D Rev. 6.2, 8/2003 MPC860 Family Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC860 family. This document contains the following topics: Topic Section 1, “Overview” Section ...

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... It particularly excels in both communications and networking systems. The PowerQUICC unit is referred to as the MPC860 in this manual. The MPC860 is a derivative of Motorola’s MC68360 Quad Integrated Communications Controller ™ (QUICC ), referred to here as the QUICC, that implements the PowerPC architecture. The CPU on the ...

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... Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG) • Interrupts — Seven external interrupt request (IRQ) lines — 12 port pins with interrupt capability MOTOROLA MPC860 Family Hardware Specifications Features 3 ...

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... HDLC/SDLC (all channels supported at 2 Mbps) — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART 4 MPC860 Family Hardware Specifications GRACEFUL STOP TRANSMIT ) , ENTER HUNT MOTOROLA ...

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... Power down mode— all units powered down, except PLL, RTC, PIT, time base, and decrementer • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = ≠ < > MOTOROLA MPC860 Family Hardware Specifications Features 5 ...

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... Table 2. Maximum Tolerated Ratings Symbol V DDH V DDL KAPWR VDDSYN A(min) T j(max) T A(min) T j(max) T stg . Maximum temperatures are guaranteed Value Unit –0.3 to 4.0 V –0.3 to 4.0 V –0.3 to 4.0 V –0.3 to 4.0 V GND – 0.3 to VDDH V 0 ˚C 95 ˚C –40 ˚C 95 ˚C –55 to 150 ˚C MOTOROLA ...

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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. MOTOROLA MPC860 Family Hardware Specifications Environment Symbol Single layer board (1s) R θ ...

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... Table 4. Power Dissipation ( Frequency (MHz) Typical 25 450 40 700 50 870 33 375 50 575 66 750 50 656 66 TBD 66 722 80 851 NOTE -based power dissipation and do not DDL . I/O power dissipation varies DDH ) 2 Maximum Unit 550 mW 850 mW 1050 mW TBD mW TBD mW TBD mW 735 mW TBD mW 762 mW 909 mW MOTOROLA ...

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... Output Low Voltage IOL = 2.0 mA, CLKOUT 2 IOL = 3 IOL = 5.3 mA IOL = 7.0 mA, TXD1/PA14, TXD2/PA12 IOL = 8.9 mA, TS, TA, TEA, BI, BB, HRESET, SRESET 1 Input capacitance is periodically sampled. MOTOROLA MPC860 Family Hardware Specifications Table 5. DC Electrical Specifications Symbol VDDSYN DDH DDL KAPWR (power-down mode) ...

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... R = junction-to-ambient thermal resistance (ºC/W) θ junction-to-case thermal resistance (ºC/W) θ case-to-ambient thermal resistance (ºC/W) θCA 10 MPC860 Family Hardware Specifications × PI/O, where PI/O is the power dissipation of the I °C can be obtained from the equation: J × – are possible θCA MOTOROLA ...

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... MOTOROLA MPC860 Family Hardware Specifications Thermal Calculation and Measurement . For instance, the user can change the air flow around θ ...

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... MPC860 Family Hardware Specifications ) can be used to determine the junction temperature with a JT × power supply should be bypassed to ground using at least four 0.1 DD and GND should be kept to less than half an inch DD (415) 964-5111 800-854-7179 or 303-397-7956 http://www.jedec.org and GND planes. CC MOTOROLA ...

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... CLKOUT pulse width low B3 CLKOUT width high 3 B4 CLKOUT rise time CLKOUT fall time B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) invalid MOTOROLA MPC860 Family Hardware Specifications Table 6. Bus Operation Timings 33 MHz 40 MHz Min Max Min Max 30.30 30.30 25.00 30.30 –0.90 0.90 – ...

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... MOTOROLA ...

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... B27a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11, TRLX = 1 B28 CLKOUT rising edge to WE(0:3) negated GPCM write access CSNT = 0 B28a CLKOUT falling edge to WE(0:3) negated GPCM write access TRLX = 0, 1, CSNT = 1, EBDF = 0 MOTOROLA MPC860 Family Hardware Specifications 33 MHz 40 MHz 50 MHz Min Max Min Max Min 6 ...

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... Unit Max Min Max 11.75 — 10.54 ns 14.13 5.18 12.31 ns 14.13 — 12.31 ns — 1.79 — ns — 5.58 — ns — 1.79 — ns — 5.58 — ns — 20.73 — ns — 29.73 — ns — 3.18 — ns — 3.18 — ns — 17.83 — ns MOTOROLA ...

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... B31b CLKOUT rising edge to CS valid—as requested by control bit CST2 in the corresponding word in UPM B31c CLKOUT rising edge to CS valid—as requested by control bit CST3 in the corresponding word in UPM MOTOROLA MPC860 Family Hardware Specifications 33 MHz 40 MHz 50 MHz Min Max ...

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... Unit Max Min Max 14.13 7.58 12.31 ns 6.00 1.50 6.00 ns 11.75 3.80 10.54 ns 8.00 1.50 8.00 ns 11.75 3.80 10.54 ns 14.13 7.58 12.31 ns 6.00 1.50 6.00 ns 11.75 3.80 10.54 ns — 1.79 — ns — 5.58 — ns — 9.36 — ns — 1.79 — ns MOTOROLA ...

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... B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17. 10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 20. MOTOROLA MPC860 Family Hardware Specifications 33 MHz 40 MHz ...

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... Minimum input hold time specification. Figure 3 provides the timing for the external clock. CLKOUT 20 MPC860 Family Hardware Specifications 0 2 2.0 V 2.0 V 0 2.0 V 2.0 V 0 2.0 V 0.8 V Figure 2. Control Timing Figure 3. External Clock Timing 2 2 MOTOROLA ...

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... Figure 4. Synchronous Output Signals Timing Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MOTOROLA MPC860 Family Hardware Specifications B8 B9 B8a B9 B8b ...

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... Figure 7 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT TA D[0:31], DP[0:3] Figure 7. Input Data Timing in Normal Case 22 MPC860 Family Hardware Specifications B16 B17 B16a B17a B16b B17 B16 B17 B18 B19 MOTOROLA ...

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... Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx OE WE[0:3] D[0:31], DP[0:3] Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00) MOTOROLA MPC860 Family Hardware Specifications B20 B21 and DLT3 = 1 B12 B25 B28 B18 Bus Signal Timing B23 B26 B19 ...

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... Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] CSx OE D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) 24 MPC860 Family Hardware Specifications B12 B23 B22a B24 B25 B18 B12 B22b B22c B23 B24a B25 B18 B26 B19 B26 B19 MOTOROLA ...

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... CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MOTOROLA MPC860 Family Hardware Specifications B12 B8 B22a B27 B27a B22b B22c B18 Bus Signal Timing B23 B26 B19 25 ...

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... Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] OE D[0:31], DP[0:3] Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) 26 MPC860 Family Hardware Specifications B12 B25 B26 B8 B30 B23 B28 B29b B29 B9 MOTOROLA ...

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... CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] OE D[0:31], DP[0:3] Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MOTOROLA MPC860 Family Hardware Specifications B12 B28b B28d B25 B26 B28a B28c B8 Bus Signal Timing B30a B30c B23 B29c B29g B29a B29f ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) 28 MPC860 Family Hardware Specifications B12 B8 B22 B28b B28d B25 B8 B28a B28c B30b B30d B23 B29e B29i B29d B29h B29b B9 MOTOROLA ...

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... Figure 16 provides the timing for the external bus controlled by the UPM. CLKOUT B8 A[0:31] CSx BS_A[0:3], BS_B[0:3] B35 GPL_A[0:5], GPL_B[0:5] Figure 16. External Bus Timing (UPM Controlled Signals) MOTOROLA MPC860 Family Hardware Specifications B31a B31d B31 B31b B34 B34a B34b B32a B32d B32 ...

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... Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing 30 MPC860 Family Hardware Specifications B38 B38 MOTOROLA ...

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... Figure 20. Asynchronous External Master Memory Access Timing Figure 21 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 21. Asynchronous External Master—Control Signals Negation Timing MOTOROLA MPC860 Family Hardware Specifications B41 B42 B40 B39 B40 (GPCM Controlled— ...

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... Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines 32 MPC860 Family Hardware Specifications Table 7. Interrupt Timing All Frequencies 1 Min 6.00 2.00 3.00 3.00 4 × T CLOCKOUT I39 I40 I41 I43 I43 Unit Max — ns — ns — ns — ns — — I42 MOTOROLA ...

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... These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC860 PowerQUICC User s Manual. MOTOROLA MPC860 Family Hardware Specifications Table 8. PCMCIA Timing ...

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... Figure 24 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 24. PCMCIA Access Cycles Timing External Bus Read 34 MPC860 Family Hardware Specifications P44 P46 P45 P48 P50 P52 P53 B18 P47 P49 P51 P52 B19 MOTOROLA ...

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... PCWE, IOWR ALE D[0:31] Figure 25. PCMCIA Access Cycles Timing External Bus Write Figure 26 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 26. PCMCIA WAIT Signals Detection Timing MOTOROLA MPC860 Family Hardware Specifications P44 P46 P45 P48 P50 P52 P53 ...

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... P57 P58 P59 P60 Figure 28. PCMCIA Input Port Timing 50 MHz 66 MHz Unit Min Max Min Max — 19.00 — 19.00 ns 18.00 — 14.36 — ns 5.00 — 5.00 — ns 1.00 — 1.00 — ns MOTOROLA ...

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... Figure 29 provides the input timing for the debug port clock. DSCK D63 Figure 29. Debug Port Clock Input Timing Figure 30 provides the timing for the debug port. DSCK DSDI DSDO MOTOROLA MPC860 Family Hardware Specifications Table 10. Debug Port Timing 3 × T 1.25 × T D61 D62 D61 ...

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... MOTOROLA ...

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... Figure 32 provides the reset timing for the data bus weak drive during configuration. CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 32. Reset Timing—Data Bus Weak Drive During Configuration MOTOROLA MPC860 Family Hardware Specifications R71 R76 R73 R74 R75 ...

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... Table 12. JTAG Timing Characteristic R82 R80 R81 All Frequencies Min Max 100.00 — 40.00 — 0.00 10.00 5.00 — 25.00 — — 27.00 0.00 — — 20.00 100.00 — 40.00 — — 50.00 — 50.00 — 50.00 50.00 — 50.00 — MOTOROLA Unit ...

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... Figure 35. JTAG Test Access Port Timing Diagram TCK TRST Figure 36. JTAG TRST Timing Diagram TCK Output Signals Output Signals Output Signals Figure 37. Boundary Scan (JTAG) Timing Diagram MOTOROLA MPC860 Family Hardware Specifications J82 J83 J82 J85 J86 J87 J88 J91 J90 J92 J93 IEEE 1149 ...

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... Figure 38. PIP Rx (Interlock Mode) Timing Diagram 42 MPC860 Family Hardware Specifications Table 13. PIP/PIO Timing Characteristic All Frequencies Unit Min Max 0 — 2.5 – t3 — CLK 1.5 — CLK 1 CLK – — — CLK 5 — CLK — 2 CLK 2 — CLK 15 — ns 7.5 — ns — MOTOROLA ...

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... STBO (Output) STBI (Input) Figure 39. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 40. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 41. PIP TX (Pulse Mode) Timing Diagram MOTOROLA MPC860 Family Hardware Specifications CPM Electrical Characteristics ...

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... TA assertion to falling edge of the clock setup time (applies to external TA) CLKO (Output) DREQ (Input) Figure 43. IDMA External Requests Timing Diagram 44 MPC860 Family Hardware Specifications 29 31 Table 14. IDMA Controller Timing Characteristic 40 30 All Frequencies Unit Min Max 7 — — ns — — — — — MOTOROLA ...

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... CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 44. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 45. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MOTOROLA MPC860 Family Hardware Specifications CPM Electrical Characteristics 45 ...

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... Table 15 provides the baud rate generator timings as shown in Figure 47. Table 15. Baud Rate Generator Timing Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle 50 BRGOX Figure 47. Baud Rate Generator Timing Diagram 46 MPC860 Family Hardware Specifications 42 Characteristic All Frequencies Min Max — — 51 MOTOROLA Unit ...

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... L1RCLK, L1TCLK width high (DSC = 0) 72 L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time 73 L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time) 74 L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) 75 L1RSYNC, L1TSYNC rise/fall time MOTOROLA MPC860 Family Hardware Specifications Table 16. Timer Timing Characteristic Table 17. SI Timing ...

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... Table 17. SI Timing (continued All Frequencies Unit Min Max 17.00 — ns 13.00 — ns 10.00 45.00 ns 10.00 45.00 ns 10.00 45.00 ns 10.00 55.00 ns 10.00 55.00 ns 0.00 42.00 ns — 16.00 or MHz SYNCCLK — — ns — 30.00 ns 1.00 — L1TCL K 42.00 — ns 42.00 — ns — 0.00 ns MOTOROLA ...

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... L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RXD (Input) 76 L1ST(4-1) (Output) Figure 49. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MOTOROLA MPC860 Family Hardware Specifications 70 71a 72 RFSD BIT0 78 CPM Electrical Characteristics 79 49 ...

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... CPM Electrical Characteristics CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 50. SI Receive Timing with Double-Speed Clocking (DSC = 1) 50 MPC860 Family Hardware Specifications 72 83a RFSD=1 77 BIT0 MOTOROLA ...

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... L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) 80a L1TXD BIT0 (Output) 80 L1ST(4-1) (Output) Figure 51. SI Transmit Timing Diagram (DSC = 0) MOTOROLA MPC860 Family Hardware Specifications 70 72 TFSD CPM Electrical Characteristics ...

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... CPM Electrical Characteristics CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 52. SI Transmit Timing with Double Speed Clocking (DSC = 1) 52 MPC860 Family Hardware Specifications 72 83a 82 TFSD MOTOROLA ...

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... MOTOROLA MPC860 Family Hardware Specifications CPM Electrical Characteristics Figure 53. IDL Timing 53 ...

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... All Frequencies Min Max 0.00 SYNCCLK/3 — — 0.00 30.00 0.00 30.00 40.00 — 40.00 — 0.00 — 40.00 — MOTOROLA Unit Unit MHz ...

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... Figure 54. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 55. SCC NMSI Transmit Timing Diagram MOTOROLA MPC860 Family Hardware Specifications 102 101 100 107 102 101 100 103 105 104 CPM Electrical Characteristics ...

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... MPC860 Family Hardware Specifications 102 101 100 103 104 107 105 Figure 56. HDLC Bus Timing Diagram Table 20. Ethernet Timing Characteristic 104 All Frequencies Unit Min Max 40 — ns — — 120 ns 20 — — — ns 100 — ns — — 101 MOTOROLA ...

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... SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) Figure 57. Ethernet Collision Timing Diagram RCLK1 RxD1 (Input) RENA(CD1) (Input) Figure 58. Ethernet Receive Timing Diagram MOTOROLA MPC860 Family Hardware Specifications Table 20. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 ...

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... Figure 59. Ethernet Transmit Timing Diagram RCLK1 RxD1 0 (Input) Start Frame RSTRT (Output) Figure 60. CAM Interface Receive Start Timing Diagram REJECT Figure 61. CAM Interface REJECT Timing Diagram 58 MPC860 Family Hardware Specifications 128 121 132 1 1 BIT1 125 137 129 134 BIT2 136 MOTOROLA ...

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... SMTXD (Output) 154 SMSYNC 154 SMRXD (Input) NOTE: 1. This delay is equal to an integer number of character-length clocks. Figure 62. SMC Transparent Timing Diagram MOTOROLA MPC860 Family Hardware Specifications Table 21. SMC Transparent Timing Characteristic 151 151 150 NOTE 155 155 CPM Electrical Characteristics ...

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... Figure 63. SPI Master ( Timing Diagram 60 MPC860 Family Hardware Specifications Table 22. SPI Master Timing Characteristic 167 166 160 167 166 Data lsb 165 164 166 Data lsb All Frequencies Unit Min Max 4 1024 t cyc 2 512 t cyc 50 — — ns — — ns — — msb msb MOTOROLA ...

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... Slave clock (SPICLK) high or low time 174 Slave sequential transfer delay (does not require deselect) 175 Slave data setup time (inputs) 176 Slave data hold time (inputs) 177 Slave access time MOTOROLA MPC860 Family Hardware Specifications 167 166 160 167 166 Data 165 ...

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... Data lsb 179 181 182 Data lsb 172 170 182 181 181 182 180 msb Data 179 176 181 182 Data 171 174 178 Undef msb msb 174 178 lsb lsb MOTOROLA msb msb ...

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... SDL/SCL fall time 211 Stop condition setup time 1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2). The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1. MOTOROLA MPC860 Family Hardware Specifications 2 Table 24 Timing (SCL < 100 kH Characteristic 1 CPM Electrical Characteristics ...

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... Figure 67 Bus Timing Diagram ) Z All Frequencies Unit Min Max 0 BRGCLK/48 Hz BRGCLK/48 Hz — — — — — 0 — — — 1/(10 * fSCL) — 1/(33 * fSCL) — 208 211 Direction Min Max Unit Output — 3 — 50 MHz MOTOROLA ...

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... UTPB, SOC active delay (and PHREQ and PHSEL active delay in MPHY mode) Figure 68 shows signal timings during UTOPIA receive operations. UtpClk U5 PHREQn RxClav HighZ at MPHY RxEnb UTPB SOC MOTOROLA MPC860 Family Hardware Specifications UTOPIA AC Electrical Specifications Figure 68. UTOPIA Receive Timing Direction Min ...

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... MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold M3 MII_RX_CLK pulse width high M4 MII_RX_CLK pulse width low 66 MPC860 Family Hardware Specifications Figure 69. UTOPIA Transmit Timing Table 27. MII Receive Signal Timing HighZ at MPHY Min Max Unit 5 — — ns 35% 65% MII_RX_CL K period 35% 65% MII_RX_CL K period MOTOROLA ...

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... Table 28 provides information on the MII transmit signal timing. Num Characteristic M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low MOTOROLA MPC860 Family Hardware Specifications Table 28. MII Transmit Signal Timing FEC Electrical Characteristics M4 Min Max Unit 5 — ...

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... Table 29. MII Async Inputs Signal Timing Num Characteristic M9 MII_CRS, MII_COL minimum pulse width Figure 72 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL Figure 72. MII Async Inputs Timing Diagram 68 MPC860 Family Hardware Specifications Min 1.5 M9 Max Unit — MII_TX_CLK period MOTOROLA ...

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... M15 MII_MDC pulse width low Figure 73 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 73. MII Serial Management Channel Timing Diagram MOTOROLA MPC860 Family Hardware Specifications Characteristic M14 M10 M12 M13 FEC Electrical Characteristics ...

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... channels at 40 MHz or 2 channels at 25 MHz. 70 MPC860 Family Hardware Specifications 2 Ethernet Support Multi-Channel 1 SCCs (Mbps) HDLC Support 1 10/100 2 10 10/100 10/100 10/100 10/100 ATM Support yes yes N/A N/A Yes Yes Yes Yes N/A N/A Yes Yes Yes Yes Yes Yes MOTOROLA ...

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... MOTOROLA MPC860 Family Hardware Specifications Mechanical Data and Ordering Information Frequency Temperature (MHz) (Tj) 50 0° to 95°C XPC860DEZP50nn XPC860DTZP50nn XPC860ENZP50nn XPC860SRZP50nn XPC860TZP50nn XPC855TZP50D4 66 0° to 95°C XPC860DEZP66nn XPC860DTZP66nn XPC860ENZP66nn XPC860SRZP66nn XPC860TZP66nn XPC855TZP66D4 80 0° to 95°C XPC860DEZP80nn XPC860DTZP80nn XPC860ENZP80nn ...

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... Mechanical Data and Ordering Information Table 33. MPC860P Package/Frequency Availability (continued) Ball grid array (CZP suffix) 1 Where nn specifies version D.3 (as D3) or D.4 (as D4). 72 MPC860 Family Hardware Specifications 50 –40° to 95°C XPC860DPCZP50nn XPC860PCZP50nn 66 –40° to 95°C XPC860DPCZP66nn XPC860PCZP66nn MOTOROLA ...

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... N/C PB30 PA15 PB31 A3 A9 A12 A10 A13 A11 A14 Figure 74. Pinout of the PBGA Package MOTOROLA MPC860 Family Hardware Specifications Mechanical Data and Ordering Information VDDL D6 D27 D10 D14 D18 D20 D24 D8 D23 D11 D16 D19 D21 D26 D17 D9 D15 ...

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... For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, please refer to Motorola Application Note, Plastic Ball Grid Array (order number: AN1231/D), available from your local Motorola sales office. Figure 75 shows the mechanical dimensions of the PBGA package ...

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... Changed B28a through B28d and B29d to show that TRLX can • Changed reference documentation to reflect the Rev 2 MPC860 PowerQUICC Family Users Manual. • Nontechnical reformatting MOTOROLA MPC860 Family Hardware Specifications Table 34. Document Revision History Change Document Revision History ...

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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its offi ...