MPC931 Motorola, MPC931 Datasheet
MPC931
Specifications of MPC931
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MPC931 Summary of contents
Page 1
... Both devices offer an LVCMOS input that can be used as the PLL reference. In addition the MPC931 replaces the crystal oscillator inputs with a differential PECL reference clock input that allows the device to be used in mixed technology clock distribution trees. ...
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... MPC930 MPC931 GNDO 25 Qa1 26 Qa0 27 VCCO 28 MPC930/ MPC931 Div_Sela 29 Div_Selb 30 Div_Selc Figure 1. 32–Lead Pinout (Top View) (Pullup) Power_Dn (Pullup) PLL_En (Pulldown) TCLK_Sel (Pullup) TCLK MPC930 xtal1 xtal OSC xtal2 Ext_FB (Pullup) (Pulldown) ExtFB_Sel (Pulldown) Div_Sela (Pulldown) Div_Selb (Pullup) Shut_Dn0 (Pullup) ...
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... VCO VCO/2 Power_Dn SHUT_DN0 SHUT_DN1 SHUT_DN0 SHUT_DN1 TIMING SOLUTIONS BR1333 — Rev 6 Figure 3. Power_Dn Timing Diagram Figure 4. Shut_Dn Timing Diagram 3 MPC930 MPC931 MOTOROLA ...
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... MPC930 MPC931 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter V CC Supply Voltage V I Input Voltage I IN Input Current T Stor Storage Temperature Range * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied ...
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... Maximum PLL Lock Time 4. Measured with termination. 5. See Applications Info section for more Crystal specifications. 6. See Applications Info section for more jitter information. 7. Input reference frequency is bounded by VCO lock range and feedback divide selection. MPC931 AC CHARACTERISTICS ( 3.3V 5%) Symbol Characteristic f ref Input Reference Frequency t os Output– ...
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... MPC930 MPC931 Programming the MPC930/931 The MPC930/931 clock driver outputs can be configured into several frequency relationships, in addition the external feedback option allows for a great deal of flexibility in establishing unique input to output frequency relationships. The output dividers for the three output groups allows the user to configure the outputs into 1:1, 2:1, 3:1, 3:2 and 3:2:1 frequency ratios ...
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... CMOS fanout buffers. To minimize part–to–part skew the external feedback option again should be used. The PLL in the MPC931 decouples the delay of the device from the propagation delay variations of the internal gates. From the specification table one sees a Tpd variation of only 150ps, thus for multiple devices under identical configurations the part– ...
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... For devices that are configured differently the differences between the nominal delays must also be accounted for. When using the MPC931 as a zero delay buffer there is more information which can help minimize the overall timing uncertainty. To fully minimize the specified uncertainty crucial that the relative position of the outputs be known ...
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... The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. 9 MPC930 MPC931 3. =10– 0. meet the voltage drop criteria ...
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... MPC930 MPC931 Although the MPC930/931 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs ...
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... 3.0 (25 / (21 25) = 3.0 (25 / 53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 11 MPC930 MPC931 OutA OutB0 OutB1 MOTOROLA ...
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... MPC930 MPC931 3.0 OutA 3.8956 OutB 2 3.9386 2.0 In 1.5 1.0 0 TIME (nS) Figure 17. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To MOTOROLA better match the impedances when driving multiple lines the situation in Figure 18 should be used ...
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... N É É É É É É SECTION AE– MPC930 MPC931 DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...
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... MPC930 MPC931 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...