IDT77301L12PF Integrated Device Technology, Inc., IDT77301L12PF Datasheet
IDT77301L12PF
Specifications of IDT77301L12PF
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IDT77301L12PF Summary of contents
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... SOCR CLAVR Data (D0-D17) WCLK ©2001 Integrated Device Technology, Inc. The IDT77301 UtopiaFIFO is a high-speed, low power single input port supplying four demultiplexing FIFO output ports. Each of the four output synchronous (clocked) FIFOs are 64 words (128 bytes) in depth. Data is written to the input port in “cells” (fixed length data packets). The cell size is programmable from 16 bytes to 128 bytes ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO additional logic required.) Utopia 1 signalling protocol is supported for these ports. Data can be read from each FIFO output port independently. Separate input and output port clocks are ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Symbol Name I/O 1-2, 4-8, DATA-b O 10, 100 11 SOCS CLAVS I/O 14, 16-20, DATA-c O 22-24 25 SOCS CLAVS-c I ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Symbol Name I/O 54, 56 Data 9- P_ID 0-1 57-64, 66 Data 0 69-73 ADR0 BSS I 67 WCLK I 76 BNE ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Symbol V Terminal Voltage with respect to ground TERM T Operating Temperature A T-Bias Temperature under Bias T-STG Storage Temperature I DC Output Current OUT Symbol V Commercial Supply ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load 50 I Figure 1: AC Test Load 6 5 ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO TX/RX Mode Symbol f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time CLKL (1) ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Device ID ADR(4:0) FIFO port 0 000xx 1 001xx 2 010xx 3 011xx 4 100xx 5 101xx x = Don't Care 6 110xx 7 111xx FIFO(s) Selected ADR3 ADR2 ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Switch CLAVR SOCR 18 DATA Figure 2a. In-Band Routing, Single Device Implementation Switch CLAVR SOCR 18 Figure 2b. Out-Band Routing, Single Device Implementation RMS MAS ADR0-4 5 ENR RMS ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Data is transferred in “cells”; for ATM, cell size is 53/54 bytes 16-bit bus. The UtopiaFIFO can be programmed through the cell size selection registers to ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO RCLK (I) CLAVS (I) tPENS (O) SOCS (O) Data (O) RCLK (I) CLAVS (I) ENS (O) SOCS ( LB-7 LB-6 LB-5 Data (O) Figure 5. UtopiaFIFO Tx ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO transferred, ENS is asserted, data is placed on the bus and SOCS is set HIGH for the first 9-bit word transfer. ENS will remain LOW and data transfer will ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO ENR is again asserted, the next data byte will be placed in the appropriate place in memory (no bad data or address will be written). If desired, the sender ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO WCLK (I) Address/ LB (I) 1 data CLAVR (O) (I) (I) SOCR Note: RMS = High, MAS = Low WCLK (I) Address/ A (I) B1 ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO WCLK (I) Address ( CLAVR (O) (I) SOCR (I) Data H1 (I) H2 Note: RMS = MAS = Low WCLK (I) A ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO and is available.) A new FIFO location can only be selected after current cell transfer is complete. During cell transfer, FIFO “polling” can take place. At any time when ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO WCLK (I) Address ( CLAVR ( (I) (I) SOCR Data ( Note: RMS = MAS = Low ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO ATM Layer TxData(15:0) SOCS CLAVS1 CLAVS2 CLAVS8 Figure 14. In-Band Routing, Building Block Mode (Singlecast) Commercial and Industrial Temperature Ranges #1 ADR(4:0) SOCR CLAVR Data(17:0) RMS MAS BSS #2 ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO ATM Layer TxData(15:0) SOCS CLAVS1 CLAVS2 CLAVS8 Figure 15. In-Band Routing, Building Block Mode (Multicast System) Commercial and Industrial Temperature Ranges ADR(4:0) SOCR CLAVR Data(17:0) RMS MAS BSS #2 ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO the CLAVR is asserted. On the next clock cycle, SOCR goes HIGH to indicate the start of the next cell. Changing FIFO destinations result in only a one clock ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO data that the data will be in order. The SOCR signal is directed to all UtopiaFIFOs and there are separate ENR and CLAVR signals for each pair of UtopiaFIFOs. ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO ATM Layer TxData(15:0) Address SOCS CLAVS1 CLAVS2 CLAVS8 Figure 16. Out-Band Routing, Building Block Mode (Singlecast) Commercial and Industrial Temperature Ranges #1 ADR(4:0) SOCR CLAVR Data(17:0) RMS MAS BSS ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO ATM Layer TxData(15:0) Address CLAVS1 CLAVS2 CLAVS8 Figure 17. Out-Band Routing, Building Block Mode Multicast Commercial and Industrial Temperature Ranges Port_A #1 AD R(4:0) SO ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Switch SOCR CLAVR1-A CLAVR1-B CLAVR2-A CLAVR2-B CLAVR3-A CLAVR3-B • • • • CLAVR8-A CLAVR8 • • • • 8 Commercial and Industrial Temperature Ranges CLAVR • ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO Switch SOCR CLAVR • • • • Commercial and Industrial Temperature Ranges CLAVR • SOCR • • CLAVR SOCR • • • CLAVR • SOCR • • • • ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO D0-D3 D4-D7 D8 D9-D12 D13-D16 D17 D18-D21 D22-D25 D26 D27-D30 D31-D34 D35 Commercial and Industrial Temperature Ranges Figure 20. Single Cast Mode 26 D0-3 D4-7 D9-12 D13-16 D8 D17 ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO FIFO D FIFO C FIFO B BNE MSE Q 0-3 FIFO 4 Master (Bank A) SOCS CLAVS FIFO D FIFO C FIFO B ...
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IDT77301 UtopiaFIFO™ (128 Demultiplexer-FIFO RCLK (I) CLAVS (0) Q7 (master) ENS (I) (slave) ENS (0) (master) (0) Data Q0-3 (master) (0) Data Q0-3 (slave) Data Q8 (master) (0) (0) Data Q8 (slave) Figure ...
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... Changed datasheet design format 3/26/01: Changed Preliminary to Final Electrical Characteristics Table, changed maximum from for pins t CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. NNN A A Process/ Speed Package Temp. Range ...