CXA3026Q Sony, CXA3026Q Datasheet
CXA3026Q
Specifications of CXA3026Q
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CXA3026Q Summary of contents
Page 1
... Flash A/D Converter Description The CXA3026Q is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 120MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. ...
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... / DGND3 – 1.05 DGND3 – 0 DGND3 – 3.2 DGND3 – 1.4 IL /T, INV 2 DGND1 IL /E – N/E|) 0.4 0.8 100 120 –20 VID – 2 – CXA3026Q Unit °C W Max. Min. Typ. Max. +5.25 +4.75 +5.0 +5.25 +0.05 –0.05 0 +0.05 +5.25 –0. ...
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... RESETN/E RESET AGND INV 6bits 8bits 6bits 8bits 6bits 6bits Delay D Q Select SELECT DGND1 DGND2 – 3 – CXA3026Q DGND3 12 (MSB) 40 P1D7 39 P1D6 38 P1D5 37 P1D4 36 P1D3 35 P1D2 34 P1D1 33 P1D0 (LSB) (MSB) 28 P2D7 27 P2D6 26 P2D5 25 P2D4 24 P2D3 23 P2D2 P2D1 22 21 P2D0 (LSB) ...
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... Reset input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset RESETN/E complementary input When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. – 4 – CXA3026Q Description ...
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... Comparator 255 – 5 – CXA3026Q Description Clock input. Reset input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. Data output polarity inversion input. When left open, this input goes to high level ...
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... Symbol I/O voltage level No P1D0 P1D7 21 P2D0 TTL 28 P2D7 43 CLKOUT O Equivalent circuit Comparator Vref 6 AGND CC2 DGND2 D 3 DGND1 VEE – 6 – CXA3026Q Description Analog input. Port 1 side data output. Port 2 side data output. Clock output. (See Table 2. Operating Mode Table.) ...
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... OL DMUX mode CLK CLK RESETN – CLK RESETN – CLK (C = 5pF) L DMUX mode (C = 5pF 5pF) L 0 5pF) L 0 5pF) L – 7 – CXA3026Q 25° Min. Typ. Max. Unit 8 bits ±0.5 LSB ±0.5 LSB 500 µA 75 115 155 9 ...
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... Fc = 120MSPS, { fin = 29.999MHz Fs DMUX mode Error > 16LSB Fc = 100MSPS, { fin = 24.999MHz Fs Straight mode Error > 16LSB and INV – 8 – CXA3026Q Min. Typ. Max. Unit 150 MHz –12 TPS 6 10 –9 TPS 10 –9 TPS 125 145 185 mA 0.4 0.6 0.8 mA 660 760 960 ...
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... Taj is: Taj = / 8 Latch CLK + Latch 16LSB 1/8 – 9 – CXA3026Q Amp Logic CXA3026Q Analizer CLK 1024 samples ECL Buffer 129 128 t (LSB) ...
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... Description of Operating Modes The CXA3026Q has two types of operating modes which are selected with Pin 45 (SELECT). Operating Maximum SELECT mode conversion rate DMUX mode V 120MSPS CC Straight mode GND 100MSPS 1. DMUX mode (See Application Circuit 1-(1), (2) and (3).) Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock ...
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... The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3026Q supports ECL, PECL and TTL levels. The power supplies (DV 3, DGND3) for the logic input block must be set to match the logic input (CLK and EE RESET signals) level ...
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... Digital Data +5V(D) +5V( P1D0 to P1D7 8-bit Digital Data P2D0 to P2D7 8-bit Digital Data +5V(D) – 12 – CXA3026Q 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch ...
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... Straight TTL input TTL-CLK +5V( P1D0 to P1D7 8-bit Digital Data ECL TTL DG +5V(D) +5V( P1D0 to P1D7 8-bit Digital Data PECL TTL DG +5V(D) +5V( P1D0 to P1D7 36 8-bit Digital Data +5V(D) – 13 – CXA3026Q 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch ...
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... AG 1µF AG 10µ Short the analog system and digital system at one point immediately under the A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. – 14 – CXA3026Q RESETN/E 47 RESET/E 46 RESETN/T 45 SELECT 44 INV 43 CLKOUT DGND2 40 P1D7 39 P1D6 38 P1D5 ...
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... T_rh T_rs T_rh RESET signal ) Td_clk; 7ns (typ.) 8ns (max.) 4.5ns (min.) 2.0V 2.0V (Reset period) 0.8V 0.8V 4.5ns (min.) 8ns (max.) T_rs Td_clk – 15 – CXA3026Q Tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) 2. 0.8V 2. 0.8V Tdo1 1ns (typ.) 2.0V 0.8V ...
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... Tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) P1D0 – 4 P2D0 – 5 Td_clk; 7ns (typ.) 4.5ns (min.) 8ns (max.) CLK OUT (CLK is inverted and output.) RESET signal Tpw0 2.0V N – – 2 0.8V 2.0V N – – 3 0.8V 2.0V 0.8V – 16 – CXA3026Q – – – 1 ...
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... P2D/out CLK OUT 8bit P1D/out 8bit P2D/out CLK OUT 8bit P1D/out 8bit P2D/out CLK OUT 8ns Td_clk (min.) 5.0ns <4.5ns> Td_clk (max.) 7.5ns <8.0ns> Tdo2 (min.) 7.0ns <6.5ns> Tdo2 (min.) 9.5ns <10ns> – 17 – CXA3026Q ts (min.) th (min.) 3.5ns 7.5ns 16ns ...
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... Notes on Operation • The CXA3026Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation ...
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... Analog input voltage [V] Current consumption vs. Conversion rate characteristics response 170 160 150 140 130 – Conversion rate [MSPS] Reference current vs. Ambient temperature characteristics –25 Ta – Ambient temperature [°C] – 19 – CXA3026Q f CLK fin = – 1kHz 4 DMUX mode C = 5pF L 60 120 25 75 ...
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... Error > 16LSB –9 Error rate: 10 TPS 150 140 130 – – Ambient temperature [°C] Error rate vs. Conversion rate characteristics – CLK fin = – 1kHz 4 –7 10 Error > 16LSB –8 10 –9 10 – 120 Fc – Conversion rate [MSPS] 75 – 20 – CXA3026Q 140 160 ...
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... The CXA3026Q Evaluation Board is a special board designed to maximize and facilitate the evaluation performance of the CXA3026Q. After latching the CXA3026Q output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be extracted externally via a 24-pin cable connector ...
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... CXA3026Q ...
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... DIR.IN 7. S2: Setting junction for the clock frequency division ratio. The operating speed after latching is determined by the frequency division ratio set here. When set to CLK OUT, it operates according to the CXA3026Q clock output. 8. SW1 SELECT: CXA3026Q output mode selector switch. 9. SW2 A/D INV: CXA3026Q output polarity inversion switch ...
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... In the evaluation board of the CXA3026Q, CLC404 (Comlinear) is employed for IC2 to drive the analog input signal. Though, CLC505 (Comlinear) can also be used instead of CLC404, there should be a little change in the peripheral circuit in this case. ...
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... CXA3026Q Evaluation Board Timing Chart N CON2 2Vp-p DIR IN CON3 1Vp-p CLK IN CXA3026Q CLK (PECL) CXA3026Q N – side DATA (TTL) Approximately 6.0ns CON7 P1 side DATA CLK (TTL) Approximately 9.0ns CON7 P1 side DATA N – 6 DATA (TTL) N – 6 CON4 P1 side OUT (Analog regeneration waveform – ...
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... D/A INV SW2 A/D INV DV CC SW1 DGND SELECT C29 0.1µ P1D3 36 EE P1D2 35 P1D1 34 1 P1D0 33 DGND2 IC1 CXA3026Q DGND1 P2D7 28 P2D6 27 P2D5 26 P2D4 C30 0.1µ R28 R29 82 82 R30 82 DGND R27 130 DGND R25 R26 130 130 CLK ...
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... C39 IC15 0.1µF 74ALS34 P2D7 9 8 P2D6 11 10 P2D5 13 12 P2D4 1 2 P2D3 3 4 P2D2 5 6 P2D1 9 8 P2D0 11 10 IC16 74ALS34 25 26 DGND – 27 – CXA3026Q C51 R4 MSB AGND 1 28 0.1µ VREF C52 0.1µ IC12 CX20201 ...
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... Tantal capacitor 1µF C15 Ceramic capacitor 0.1µF All parts other than those listed above Chip capacitor 0.1µF CON7 and 8 are not mounted when boards are shipped. (Manufacturer: YAMAICHI Electronics Co., Ltd.) CXA3026Q/AQ EVALUATION BOARD No R46 to 50 R6, 18, 19 R7.8 TTL conversion ...
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... Component side pattern diagram Solder side pattern diagram – 29 – CXA3026Q ...
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... M 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-48P-L04 LEAD MATERIAL QFP048-P-1212-B PACKAGE WEIGHT – 30 – CXA3026Q + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 + 0.35 EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g ...