TTSI4K32T3BAL Agere Systems, TTSI4K32T3BAL Datasheet - Page 4

• Manufacturer Part Number: TTSI4K32T3BAL
• Description: 4096-channel, 32-highway time-slot interchager
• Manufacturer: Agere Systems

TTSI4K32T
Data Sheet
4096-Channel, 32-Highway Time-Slot Interchanger
June 2000
List of Tables
Tables
Page
Table 1. Data Rate and Switch Size Examples ....................................................................................................... 5
Table 2. Pin Assignments for a 217-Pin PBGA—Pin Number Order ...................................................................... 8
Table 3. Pin Assignments for a 217-Pin PBGA—Signal Name Order................................................................... 10
Table 4. TTSI4K32T Pin Descriptions ................................................................................................................... 12
Table 5. The TSI Family ........................................................................................................................................ 17
Table 6. Time-Slot Separation Required for Transmission with Minimum Latency (0 Offsets) ............................. 24
Table 7. Offset Difference and Its Effect on Frame for Transmission.................................................................... 26
Table 8. Offset Difference Boundaries .................................................................................................................. 26
Table 9. TAP Controller States in the Data Register Branch................................................................................. 32
Table 10. TAP Controller States in the Instruction Register Branch...................................................................... 32
Table 11. TTSI2K32T’s Boundary-Scan Instructions ............................................................................................ 33
Table 12. TTSI4K32T Register Summary ............................................................................................................. 35
Table 13. General Command Register (0x00) ...................................................................................................... 37
Table 14. Software Reset Register (0x01) ............................................................................................................ 38
Table 15. BIST Command Register (0x02) ........................................................................................................... 38
Table 16. Idle Code 1 Register (0x03)................................................................................................................... 39
Table 17. Idle Code 2 Register (0x04)................................................................................................................... 39
Table 18. Idle Code 3 Register (0x05)................................................................................................................... 39
Table 19. Global Interrupt Mask Register (0x06)................................................................................................... 39
Table 20. Interrupt Status Register (0x07) ............................................................................................................ 40
Table 21. Interrupt Mask Register (0x08) .............................................................................................................. 41
Table 22. Test Command Register (0x09) ............................................................................................................ 42
Table 23. Test-Pattern Style Register (0x0A)........................................................................................................ 43
Table 24. Test-Pattern Checker Highway Register (0x0B).................................................................................... 44
Table 25. Test-Pattern Checker Upper Time-Slot Register (0x0C) ....................................................................... 44
Table 26. Test-Pattern Checker Lower Time-Slot Register (0x0D) ....................................................................... 44
Table 27. Test-Pattern Checker Data Register (0x0E).......................................................................................... 44
Table 28. Test-Pattern Error Injection Register (0x0F).......................................................................................... 44
Table 29. Test-Pattern Error Counter (Byte 0) (0x10) ........................................................................................... 45
Table 30. Test-Pattern Error Counter (Byte 1) (0x11) ........................................................................................... 45
Table 31. Test-Pattern Generator Data Register (0x12) ....................................................................................... 45
Table 32. Version Register (0x13)......................................................................................................................... 45
Table 33. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i) ......................................................... 46
Table 34. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i) ......................................................... 47
Table 35. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i) ......................................................... 47
Table 36. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i) .......................................................... 48
Table 37. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i) .......................................................... 49
Table 38. Receive Highway Configuration Register (Byte 2) (0x1802 + 4i) .......................................................... 49
Table 39. Transmit Highway 3-State Options........................................................................................................ 50
Table 40. Address Scheme for Data Store Memory ............................................................................................. 51
Table 41. Address Scheme for Connection Store Memory .................................................................................. 51
Table 42. Connection Store Memory (Byte 0) ....................................................................................................... 52
Table 43. Connection Store Memory (Byte 1) ....................................................................................................... 52
Table 44. Clock Specifications .............................................................................................................................. 55
Table 45. Asynchronous Read and Write Interface Timing Using DT Handshake................................................ 56
Table 46. Asynchronous Microprocessor Interface Timing Using Only CS .......................................................... 57
Table 47. Synchronous Microprocessor Interface Timing ..................................................................................... 59
Table 48. TDM Highway Timing ............................................................................................................................ 60
Table 49. JTAG Interface Timing........................................................................................................................... 61
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Lucent Technologies Inc.