MPC9653A Motorola, MPC9653A Datasheet
MPC9653A
Specifications of MPC9653A
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MPC9653A Summary of contents
Page 1
... VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running at either the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F The MPC9653A has a differential LVPECL reference input along with an external feedback input ...
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... CC 3⋅25k PLL_EN VCO_SEL BYPASS MR/OE 25k GND Q0 VCC QFB GND PLL_EN BYPASS VCO_SEL Figure 2. MPC9653A 32-Lead Package Pinout (Top View) 2 Freescale Semiconductor, Inc. ÷ Ref 1 1 ÷2 VCO PLL* 200-500 MHz FB * PLL will lock @ 145 MHz Figure 1. MPC9653A Logic Diagram ...
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... Default PLL_EN Test mode with PLL bypassed. The reference clock (PCLK substituted for the internal VCO output. MPC9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. BYPASS Test mode with PLL and output dividers bypassed. The 1 reference clock (PCLK) is directly routed to the outputs ...
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... V (DC) specification. PP The MPC9653A is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission b. . Alternatively, the device drives up to two 50 Ω series terminated transmission lines. The MPC9653A meets line to a termination voltage of V ...
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... PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, b. ÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN= bypass mode, the MPC9653A divides the input reference clock. e. The input frequency f must match the VCO frequency range divided by the feedback divider ratio FB: f REF f ...
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... CMOS fanout buffers. The external feedback option of the MPC9653A clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the de- ...
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... Figure 6, “Single versus Dual Transmission Lines”, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9653A clock driver is effectively doubled due to its capability to drive multiple lines. ...
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... Termination Waveforms”, show the simulation results of an out- put driving a single line versus two lines. In both cases the drive capability of the MPC9653A output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs ...
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... PCLK ÷ GND FB_IN x 100% 0 The deviation in t random sample of cycles = | N+1 The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles = 3 2.4 0.55 Go to: www.freescale.com MPC9653A 0 CMR GND t (PD) , static phase offset) (PD) test reference mean| JIT(∅ ...
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... MPC9653A/D D1 D1/2 PIN 1 INDEX E1 DETAIL D 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ ( (L1) DETAIL AD 10 Freescale Semiconductor, Inc. OUTLINE DIMENSIONS 4X 0. 32X 0.1 C BASE PLATING METAL 0. SECTION F 0.25 GAUGE PLANE θ˚ FA SUFFIX CASE 873A-03 ISSUE B LQFP PACKAGE ...
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... Freescale Semiconductor, Inc. TIMING SOLUTIONS For More Information On This Product, NOTES Go to: www.freescale.com MPC9653A/D 11 ...
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... JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong For More Information On This Product, Go to: www.freescale.com 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 852-26668334 HOME PAGE: http://motorola.com/semiconductors MPC9653A/D ...