SAA5284GP Philips Semiconductors, SAA5284GP Datasheet
SAA5284GP
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DATA SHEET SAA5284 Multimedia video data acquisition circuit Objective specification Supersedes data of 1997 Mar 03 File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1998 Feb 05 ...
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... Philips Semiconductors Multimedia video data acquisition circuit CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 MAIN FUNCTIONAL BLOCKS 6 BLOCK DIAGRAM 7 PINNING INFORMATION 7.1 Pinning 7.2 Pin description 8 FUNCTIONAL DESCRIPTION 8.1 Power supply strategy 8.2 Clocking strategy 8.3 Power-on reset 8.4 Analog switch 8 ...
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... Note 1. Selectable: 12, 13. MHz. 4 ORDERING INFORMATION TYPE NUMBER NAME SAA5284GP QFP44 1998 Feb 05 Single IC with few external components and small footprint QFP44 package Optimized for EMC. 2 GENERAL DESCRIPTION The SAA5284 is a Vertical Blanking Interval (VBI) and Full ...
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... Philips Semiconductors Multimedia video data acquisition circuit 5 MAIN FUNCTIONAL BLOCKS 1. Input clamp and sync separator 2. Analog-to-digital converter 3. Multi-standard data slicer and clock regenerator 4. Packet filtering; (8 and 4) Hamming correction 5. On-chip data cache 6. Line selectable data type 6 BLOCK DIAGRAM handbook, full pagewidth V DDA V SSA V DDX V DDD V SSD3 ...
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... Philips Semiconductors Multimedia video data acquisition circuit 7 PINNING INFORMATION 7.1 Pinning handbook, full pagewidth RESET HREF SDA SCL DENB V DDX OSCOUT OSCIN OSCGND SEL0 SEL1 (1) Multi-functional pin. 7.2 Pin description Table 1 QFP44 package The IC has a total of 44 pins; many of these are multi-functional due to the multiple host block modes of operation. ...
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... Philips Semiconductors Multimedia video data acquisition circuit SYMBOL PIN OSCGND 9 SEL0 10 SEL1 11 BLACK REF CVBS1 14 CVBS0 DDA V 17 SSA V 18 SSD1 V 19 SSD2 ( ( ( ( ( ( ( ( ( ( ( INT 31 (1) RDY CS0 35 DMARQ 36 (1) DMACK 37 VPOIN0 38 VPOIN1 SSD3 V 41 DDD LLC 42 LLC2 43 CS1 44 Note 1. These pins have two functions, depending on the interface mode. ...
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... Philips Semiconductors Multimedia video data acquisition circuit 8 FUNCTIONAL DESCRIPTION 8.1 Power supply strategy There are three separate + supplies the critical noise-sensitive analog DDA front-end sections: ADC and sync separator, to reduce interference from the rest of the front-end 2. V supplies all sections which take standing DC ...
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... Philips Semiconductors Multimedia video data acquisition circuit 8.9 Host interface The SAA5284 has a multi-standard 8-bit I/O interface. To reduce the amount of host I/O space used, the parallel interface has only 3 address inputs (A0, A1 and A2). An extended addressing (pointer) scheme and the data FIFO are used to allow access to the full set of SAA5284 registers and the full span of the packet buffer ...
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... Philips Semiconductors Multimedia video data acquisition circuit 11 CHARACTERISTICS + 4.5 to 5.5 V; unless otherwise specified. amb DD SYMBOL PARAMETER Power supply V supply voltage DDn I total supply current DD(tot) I digital supply current DDD I analog supply current DDA Inputs CVBS0 and CVBS1 V sync voltage sync(p-p) ...
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... Philips Semiconductors Multimedia video data acquisition circuit SYMBOL PARAMETER Input/output SDA (open-drain) V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI C input capacitance i t input rise time i(r) t input fall time i(f) V LOW-level output voltage OL t output fall time ...
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... Philips Semiconductors Multimedia video data acquisition circuit SYMBOL PARAMETER 2 I C-bus timings (see note 2 and Fig.8) f SCL input clock frequency i(SCL) t SCL LOW time LOW t SCL HIGH time HIGH t data set-up time SU;DAT t data hold time HD;DAT t set-up time STOP condition SU ...
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... Philips Semiconductors Multimedia video data acquisition circuit 12 TIMING handbook, full pagewidth 3-state CS0 or CS1 RD RDY (1) Event A occurs when RD + CS0 + CS1 = 0 (boolean). (2) Event B occurs when RD + CS0 + CS1 = 1 (boolean). Table 3 Intel-mode interface read cycle timing (12 MHz clock) SYMBOL t minimum cycle time 0 t address set-up time before event A ...
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... Philips Semiconductors Multimedia video data acquisition circuit handbook, full pagewidth CS0 or CS1 WR RDY (1) Event A occurs when WR + CS0 + CS1 = 0 (boolean). (2) Event B occurs when WR + CS0 + CS1 = 1 (boolean). Table 4 Intel-mode interface write cycle timing (12 MHz clock) SYMBOL t minimum cycle time 0 t address set-up time ...
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... Philips Semiconductors Multimedia video data acquisition circuit handbook, full pagewidth DMARQ DMACK CS (same signal as DMACK) ( (1) Read data pipelined LOW to data valid set-up time. Table 5 Intel-mode interface DMA cycle timing (12 MHz clock) SYMBOL t DMARQ to DMACK LOW to DMARQ LOW 2 t cycle time 3 t DMACK to RD active ...
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... Philips Semiconductors Multimedia video data acquisition circuit handbook, full pagewidth 3-state CS1 or CS0 R/W LDS DTACK (1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean). (2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean). Table 6 Motorola-mode interface read cycle timing (12 MHz clock) SYMBOL t minimum cycle time ...
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... Philips Semiconductors Multimedia video data acquisition circuit handbook, full pagewidth 3-state CS1 or CS0 R/W LDS DTACK (1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean). (2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean). Table 7 Motorola-mode interface write cycle timing (12 MHz clock) SYMBOL t minimum cycle time ...
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... Philips Semiconductors Multimedia video data acquisition circuit handbook, full pagewidth SCL t SU;STA SDA t BUF handbook, full pagewidth VPOIN t 0 VPOOUT CS0 or CS1 t 4 LLC LLC2 Table 8 Digital video mode interface timing with 13.5 MHz clock and 27 MHz LLC SYMBOL t VPOIN set-up time ...
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... Philips Semiconductors Multimedia video data acquisition circuit 13 APPLICATION INFORMATION 13.1 Hardware application circuit for ISA card A typical application circuit diagram (for the ISA card application) is shown in Fig.10. 13.2 Hardware application circuit for PCI application This PCI application is based around the Philips SAA7146 video to PCI bridge IC. SAA7146 has a ‘ ...
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... Philips Semiconductors Multimedia video data acquisition circuit handbook, full pagewidth 100 nF V SSA = 100 nF CVBS0 100 nF CVBS1 75 12 MHz V SSA = OSCOUT OSCGND V SSD = DDA 100 nF V SSA (1) Option of 13.5, 15 and 16 MHz or direct feed from external clock. (2) A diode recommended for ESD protection. ...
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Acrobat reader. white to force landscape pages to be ... 100 nF BLACK V SSA = REF 75 100 ...
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... Philips Semiconductors Multimedia video data acquisition circuit 14 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 2 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 2.3 mm 2.60 0.25 0.05 2.1 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors Multimedia video data acquisition circuit 15 SOLDERING 15.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities ...
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... Philips Semiconductors Multimedia video data acquisition circuit 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains fi ...
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... Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...