MC141543P Motorola, MC141543P Datasheet
MC141543P
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MC141543P Summary of contents
Page 1
... Provides a Clock Output Synchronous to the Incoming H Sync for External PWM M_BUS (IIC) Interface with Address $7A Single Positive 5 V Supply REV 2 2/97 TN97022700 MOTOROLA Motorola, Inc. 1997 Order this document by MC141543/D MC141543 P SUFFIX PLASTIC DIP CASE 648 ORDERING INFORMATION MC141543P Plastic DIP PIN ASSIGNMENT V SS( VCO DD(A ) ...
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... CCOLORS AND SELECT Î Î Î Î Î ROW Î Î Î Î Î CHS BUFFER Î Î Î Î Î CWS Î Î Î Î Î 6 CRADDR CRS CHARACTER ROMS 10–BIT SHIFT REGISTERS 13 CCOLORS COLOR ENCODER AND SELECT MOTOROLA ...
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... Input Voltage of Pin SDA and SCL in M_BUS Mode V IL Logic Low V IH Logic High I II High–Z Leakage Current ( and FBKG Input Current (Not Including RP, VCO FBKG and HTONE/PWMCK Supply Current (No Load on Any Output) 90% MOTOROLA Value Unit – – – 150 DD( ...
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... B,G,R (Pins 13,14,15) AMOSD color output is TTL level RGB to the host monitor. These three signals are active high output pins that are in a high–impedance state when AMOSD is disabled (Pin 16) This is the ground pin for the digital logic of the chip. MOTOROLA ...
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... Note that the OSD_EN bit must be set after all the display information has been sent, in order to activate the AMOSD circuitry of MC141543 so that the received information can be displayed. MOTOROLA DATA BYTES CHIP ADDRESS SDA ACK ...
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... WINDOW 1 WINDOW 2 WINDOW AND FRAME CONTROL REGISTERS Figure 5. Memory Map COLUMN DISPLAY REGISTERS WINDOW 3 FRAME CRTL REG MOTOROLA ...
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... COLN 2 MSB LSB Î Î Î Î Î Î Î Î Î Î Î Î MOTOROLA Bits 2– and B — These bits control the color of Win- dow 1. Window 1 occupies Columns 0–2 of Row 15; Window 2 occupies Columns 3–5; and Window 3 occupies Columns 6–8. Window 1 has the highest priority, and Window 3 the ...
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... Display character when CH=34 MOTOROLA ...
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... Bit X32B Bit X32B is 1 and Bit X64 is 0, the dot frequency will be 15.36 MHz (one and a half of the original one). If Bit X32B is 1 and Bit X64 is also 1, the dot frequency will be 20.48 MHz (double of the original one). MOTOROLA vertical delay = VERTD scan lines VFLB Ï ...
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... Speaker 07, 08 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ROM CONTENT Figures 10 – 13 show the ROM content of MC141543. Mask ROM is optional for custom parts. MOTOROLA ...
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... Figure 10. ROM Address ($00 – $1F) MOTOROLA Figure 11. ROM Address ($20 – $3F) MC141543 11 ...
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... Figure 12. ROM Address ($40 – $5F) MC141543 12 Figure 13. ROM Address ($60 – $7F) MOTOROLA ...
Page 13
... DESIGN CONSIDERATIONS Distortion Motorola’s MC141543P has a built–in PLL for multi–sys- tem application. Pin 2 voltage is dc–based for the internal VCO in the PLL. When the input frequency (HFLB) to Pin 5 increases, the VCO frequency will increase accordingly. This forces the PLL to a higher locked frequency output. The fre- quency should be equal to 320/480/640 x HFLB (depending on resolution) ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...