54F74 National Semiconductor, 54F74 Datasheet

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54F74

Manufacturer Part Number
54F74
Description
Dual D-Type Positive Edge-Triggered Flip-Flop
Manufacturer
National Semiconductor
Datasheet

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C 1995 National Semiconductor Corporation
54F 74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The ’F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q Q) outputs Information at the
input is transferred to the outputs on the positive edge of
the clock pulse Clock triggering occurs at a voltage level of
the clock pulse and is not directly related to the transition
time of the positive-going pulse After the Clock Pulse input
threshold voltage has been passed the Data input is locked
out and information present will not be transferred to the
outputs until the next rising edge of the Clock Pulse input
Logic Symbols
TRI-STATE is a registered trademark of National Semiconductor Corporation
Note 1 Devices also available in 13 reel Use Suffix
Note 2 Military grade device with environmental and burn-in processing Use suffix
74F74PC
74F74SC (Note 1)
74F74SJ (Note 1)
Commercial
54F74DM (Note 2)
54F74FM (Note 2)
54F74LM (Note 2)
TL F 9469–3
TL F 9469
Military
e
SCX
Package
N14A
J14A
M14A
M14D
W14B
E20A
Number
Asynchronous Inputs
Features
Y
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
Guaranteed 4000V minimum ESD protection
makes both Q and Q HIGH
e
TL F 9469 – 4
DMQB FMQB and LMQB
Package Description
D
D
sets Q to HIGH level
sets Q to LOW level
D
and S
D
IEEE IEC
RRD-B30M75 Printed in U S A
December 1994
TL F 9469 – 6

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54F74 Summary of contents

Page 1

... Note 1 Devices also available in 13 reel Use Suffix Note 2 Military grade device with environmental and burn-in processing Use suffix Logic Symbols TL F 9469–3 TRI-STATE is a registered trademark of National Semiconductor Corporation ...

Page 2

Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Unit Loading Fan Out Pin Names Description D D Data Inputs Clock Pulse Inputs (Active Rising Edge Direct Clear Inputs (Active LOW) D1 ...

Page 3

... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b Ambient Temperature under Bias b Junction Temperature under Bias b Plastic b V Pin Potential to CC Ground Pin Input Voltage (Note 2) ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency max t Propagation Delay PLH PHL Propagation Delay PLH PHL ...

Page 5

Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows Temperature Range Family 74F Commercial e 54F Military e Device Type Package Code P ...

Page 6

Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Dual-In-Line Package (D) 14-Lead (0 150 Wide) Molded Small Outline JEDEC (S) NS Package Number J14A NS Package Number M14A 6 ...

Page 7

Physical Dimensions inches (millimeters) (Continued) 14-Lead (0 300 Wide) Molded Small Outline EIAJ (SJ) 14-Lead (0 300 Wide) Molded Dual-In-Line Package (P) NS Package Number M14D NS Package Number N14A 7 ...

Page 8

... National Semiconductor National Semiconductor National Semiconductores Japan Ltd Hong Kong Ltd Do Brazil Ltda Sumitomo Chemical 13th Floor Straight Block ...

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