AM79C970AKC Advanced Micro Devices, AM79C970AKC Datasheet
AM79C970AKC
Specifications of AM79C970AKC
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AM79C970AKC Summary of contents
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... PCs, printers, fax modems, and bridge/router de- This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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AMD The PCnet-PCI II controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus interface unit, a DMA buffer management unit, an IEEE 802.3-compliant Media Access Control (MAC) function, individual 272-byte transmit and 256-byte ...
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BLOCK DIAGRAM CLK RST AD[31:00] C/BE[3:0] PAR FRAME TRDY IRDY STOP PCI Bus LOCK Interface IDSEL DEVSEL REQ GNT PERR SERR INTA NOUT SLEEP TCK JTAG TMS Port TDI Control TDO ...
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AMD TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Master Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PCI Vendor ...
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AMD CSR36: Next Next Receive Descriptor Address Lower CSR37: Next Next Receive Descriptor Address Upper CSR38: Next Next Transmit Descriptor Address Lower CSR39: Next Next Transmit Descriptor Address Upper CSR40: Current Receive Byte Count CSR41: Current Receive Status CSR42: Current ...
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RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD LAPP Rules for Parsing of Descriptors Some Examples of LAPP Descriptor Interaction Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . ...
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RELATED PRODUCTS Part No. Description Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79C900 Integrated Local Area Communications Controller (ILACC ) ...
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AMD CONNECTION DIAGRAM – 132-PIN PQFP VDDB 1 AD27 2 AD26 3 VSSB 4 AD25 5 AD24 6 C/BE3 7 VDD 8 TDI 9 IDSEL 10 VSS 11 AD23 12 AD22 13 VSSB 14 AD21 15 AD20 16 VDDB 17 ...
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CONNECTION DIAGRAM – 144-PIN TQFP NC 1 VDDB 2 AD27 3 AD26 4 VSSB 5 AD25 6 AD24 7 C/BE3 8 VDD 9 TDI 10 IDSEL 11 VSSB 12 AD23 13 AD22 14 VSSB 15 AD21 16 AD20 17 VDDB ...
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AMD PIN DESIGNATIONS – 132-PIN PQFP Listed By Pin Number Pin No. Name Pin No. 1 VDDB 34 2 AD27 35 3 AD26 36 4 VSSB 37 5 AD25 38 6 AD24 39 7 C/BE3 40 8 VDD 41 9 ...
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PIN DESIGNATIONS – 132-PIN PQFP Listed By Group Pin Name Pin Function PCI Bus Interface AD[31:0] Address/Data Bus C/BE[3:0] Bus Command/Byte Enable CLK Bus Clock DEVSEL Device Select FRAME Cycle Frame GNT Bus Grant IDSEL Initialization Device Select INTA Interrupt ...
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AMD PIN DESIGNATIONS – 132-PIN PQFP Listed By Group Pin Name Pin Function PCI Bus Interface Attachment Unit Interface (AUI) CI+/CI- AUI Collision Differential Pair DI+/DI- AUI Data In Differential Pair DO+/DO- AUI Data Out Differential Pair DXCVR Disable Transceiver ...
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PIN DESIGNATIONS – 144-PIN TQFP Listed By Pin Number Pin No. Name Pin No VDDB 38 3 AD27 39 4 AD26 40 5 VSSB 41 6 AD25 42 7 AD24 43 8 C/BE3 44 9 VDD ...
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AMD PIN DESIGNATIONS – 144-PIN TQFP Listed By Group Pin Name Pin Function PCI Bus Interface AD[31:0] Address/Data Bus C/BE[3:0] Bus Command/Byte Enable CLK Bus Clock DEVSEL Device Select FRAME Cycle Frame GNT Bus Grant IDSEL Initialization Device Select INTA ...
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PIN DESIGNATIONS – 144-PIN TQFP Listed By Group Pin Name Pin Function PCI Bus Interface Attachment Unit Interface (AUI) CI+/CI- AUI Collision Differential Pair DI+/DI- AUI Data In Differential Pair DO+/DO- AUI Data Out Differential Pair DXCVR Disable Transceiver 10BASE-T ...
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AMD PIN DESIGNATIONS Listed By Driver Type The next table describes the various types of drivers that are used in the PCnet-PCI II controller: Name Type LED LED O6 Totem Pole OD6 Open Drain TM STS6 Sustained Tri-State TS3 Tri-State ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C970A K DEVICE NUMBER/DESCRIPTION Am79C970A PCnet-PCI II Single-Chip Full-Duplex Controller for PCI Local Bus ...
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AMD PIN DESCRIPTION PCI Interface AD[31:0] Address and Data Address and data are multiplexed on the same bus in- terface pins. During the first clock of a transaction AD[31:0] contain a physical address (32 bits). During the subsequent clocks AD[31:0] ...
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INTA Interrupt Request An attention signal which indicates that one or more of the following status flags is set: BABL, EXDINT, IDON, JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, SLPINT, TINT, TXSTRT and UINT. Each status flag has either ...
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AMD H_RESET (HARDWARE_RESET). RST must be held for a minimum of 30 clock periods. While in the H_RE- SET state, the PCnet-PCI II controller will disable or deassert all outputs. RST may be asynchronous to CLK when asserted or deasserted. ...
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SLEEP pin itself. Deasser- tion of SLEEP results in wake-up. The system must re- frain from starting the network operations of the PCnet-PCI II controller device for 0.5 s following the deassertion of the ...
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AMD Expansion ROM Interface ERA[7:0] Expansion ROM Address These pins provide the address to the Expansion ROM. When EROE is asserted and ERACLK is driven HIGH, ERA[7:0] contain the upper 8 bits of the Expansion ROM address. They must be ...
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Note that the RXCLK pin is multiplexed with the ERD1 pin. RXDAT Receive Data RXDAT is an input. Rising edges of the RXCLK signal are used to sample the data on the RXDAT input when- ever the RXEN input is ...
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AMD operates in the same signaling environment as the PCI bus interface. TDI Test Data In TDI is the test data input path to the PCnet-PCI II con- troller. The pin has an internal pull-up resistor. The TDI input operates ...
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BASIC FUNCTIONS System Bus Interface Function The PCnet-PCI II controller is designed to operate as a bus master during normal operations. Some slave I/O accesses to the PCnet-PCI II controller are required in normal operations as well. Initialization of the ...
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AMD DETAILED FUNCTIONS Slave Bus Interface Unit The slave bus interface unit (BIU) controls all accesses to the PCI configuration space, the Control and Status Registers (CSR), the Bus Configuration Registers C[3:0] Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 ...
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CLK FRAME ADDR AD 1010 C/BE PAR PAR IRDY TRDY DEVSEL STOP IDSEL Figure 1. Slave Configuration Read Am79C970A DATA BE PAR ...
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AMD CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP IDSEL Slave I/O Transfers After the PCnet-PCI II controller is configured as an I/O device by setting IOEN (for regular I/O mode) or MEMEN (for memory mapped I/O mode) in ...
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ONE. The PCnet-PCI II controller is capable of detecting an I memory mapped I/O cycle even when its address phase immedi- ately follows the data phase of a transaction to a differ- ...
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AMD CLK 1 2 FRAME AD ADDR 0111 C/BE PAR PAR IRDY TRDY DEVSEL STOP Figure 4. Slave Write Using Memory Command Expansion ROM Transfers The host must initialize the Expansion ROM Base Ad- dress register at offset 30h in ...
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ONE. The PCnet-PCI II con- troller is capable of detecting a memory cycle even when its address phase immediately follows the data phase of a transaction to a different target without any CLK 1 ...
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AMD read operation by setting the PREAD bit (BCR19, bit 14). While the EEPROM read is on-going, the PCnet-PCI II controller will disconnect any slave access where it is the target by asserting STOP together with DEVSEL, while driving TRDY ...
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Disconnect Of Burst Transfer The PCnet-PCI II controller does not support burst ac- cess to the configuration space, the I/O resources the Expansion ROM. The host indicates a burst transac- tion by keeping FRAME asserted during the data ...
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AMD When the host is not yet ready when the PCnet-PCI II controller asserts TRDY, the device will wait for the host to assert IRDY. When the host asserts IRDY and FRAME is still asserted, the PCnet-PCI II controller will ...
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Disconnect When Locked When the PCnet-PCI II controller is locked by one master and another master tries to access the control- ler, the device will disconnect the access. When the PCnet-PCI II controller is in the locked state and it ...
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AMD Parity Error Response When the PCnet-PCI II controller is not the current bus master, it samples the AD[31:0], C/BE[3:0] and the PAR lines during the address phase of any PCI command for a parity error. When it detects an ...
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During the data phase of an I/O write, memory mapped I/O write or configuration write command that selects the PCnet-PCI II controller as target, the device samples the AD[31:0] and C/BE[3:0] lines for parity on the clock edge data is ...
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AMD Master Bus Interface Unit The master bus interface unit (BIU) controls the acquisition of the PCI bus and all accesses to the initialization block, descriptor rings and the receive and C[3:0] Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 ...
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CLK FRAME C/BE IRDY REQ GNT Bus Master DMA Transfers There are four primary types of DMA transfers. The PCnet-PCI II controller uses non-burst as well as burst cycles for read and write access to the main memory. Basic Non-Burst ...
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AMD The following figure shows two non-burst read transac- tions. The first transaction has zero wait states. In the CLK 1 2 FRAME AD ADDR 0110 C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Basic Burst Read Transfer ...
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The following figure shows a typical burst read access. The PCnet-PCI II controller arbitrates for the bus, is granted access, and reads three 32-bit words (DWord) from the system memory and then releases the bus. In the example, the memory ...
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AMD The following figure shows two non-burst write transac- tions. The first transaction has two wait states. The tar- get inserts one wait state by asserting DEVSEL one clock late and another wait state by also asserting TRDY CLK 1 ...
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The following figure shows a typical burst write access. The PCnet-PCI II controller arbitrates for the bus, is granted access, and writes four 32-bit words (DWords) to the system memory and then releases the bus. In this example, the memory ...
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AMD Target Initiated Termination When the PCnet-PCI II controller is a bus master, the cycles it produces on the PCI bus may be terminated by the target in one of three different ways. Disconnect With Data Transfer The figure below ...
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Disconnect Without Data Transfer The figure below shows a target disconnect sequence during which no data is transferred. STOP is asserted on clock 4 without TRDY being asserted at the same time. The PCnet-PCI II controller terminates the access with ...
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AMD Target Abort The figure below shows a target abort sequence. The target asserts DEVSEL for one clock. It then deasserts DEVSEL and asserts STOP on clock 4. A target can use the target abort sequence to indicate that it ...
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Master Initiated Termination There are three scenarios besides normal completion of a transaction where the PCnet-PCI II controller will ter- minate the cycles it produces on the PCI bus. Preemption During Non-Burst Transaction When the PCnet-PCI II controller performs multiple ...
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AMD Preemption During Burst Transaction When the PCnet-PCI II controller operates in burst mode, it only performs a single transaction per bus mas- tership period, where transaction is defined as one ad- dress phase and one or multiple data phases. ...
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Master Abort The PCnet-PCI II controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the PCnet-PCI II controller. ...
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AMD Parity Error Response During every data phase of a DMA read operation, when the target indicates that the data is valid by asserting TRDY, the PCnet-PCI II controller samples the AD[31:0], C/BE[3:0] and the PAR lines for a data ...
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All network activity continues. Advanced Parity Error Handling For all DMA cycles, the PCnet-PCI II controller provides a second, more advanced level of parity error handling. This mode is enabled by setting APERREN (BCR20, ...
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AMD Initialization Block DMA Transfers During execution of the PCnet-PCI II controller bus master initialization procedure, the PCnet-PCI II con- troller microcode will repeatedly request DMA transfers from the BIU. During each of these initialization block DMA transfers, the BIU ...
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When BREADE is set to ONE (BCR18, bit 6), all initiali- zation block read transfers will be executed in burst CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 25. Initialization Block Read In Burst Mode P R ...
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AMD Descriptor DMA Transfers PCnet-PCI II controller microcode will determine when a descriptor access is required. A descriptor DMA read will consist of two data transfers. A descriptor DMA write will consist of one or two data transfers. The descriptor ...
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CLK 1 2 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 26. Descriptor Ring Read In Non-Burst Mode During descriptor write accesses, only the byte lanes which need to be written are enabled. If buffer ...
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AMD CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 27. Descriptor Ring Read In Burst Mode The settings of SWSTYLE (BCR20, bits 7–0) and BWRITE (BCR18, bit 5) affect the way the PCnet-PCI II controller performs descriptor ...
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Note that the figure below assumes that the PCnet-PCI II controller is programmed to use 32-bit software structures (SWSTYLE = 3). The byte CLK 1 2 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is ...
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AMD CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 29. Descriptor Ring Write In Burst Mode FIFO DMA Transfers PCnet-PCI II controller microcode will determine when a FIFO DMA transfer is required. This ...
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DMA Bus Activity Timer (CSR82) has expired. The exact number of total transfer cycles in the bus mastership period is depend- ent on all of the following variables: the settings of the FIFO watermarks, ...
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AMD The following figure shows the beginning of a FIFO DMA write with the beginning of the buffer not aligned to a DWord boundary. The PCnet-PCI II controller starts off by writing only three bytes during the first data phase. ...
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If a receive buffer does not end on a DWord boundary, the PCnet-PCI II controller will perform a non-DWord write on the last transfer to the buffer. The following fig- ure shows the final three FIFO DMA transfers to a ...
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AMD In applications that don’t use the PCI Latency Timer or that don’t support preemption the following rules apply to limit the time the PCnet-PCI II controller takes up on the bus. If DMAPLUS is cleared to ZERO, a maximum ...
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CSR15, and then setting the START bit in CSR0. Note that this form of restart will not perform the same in the PCnet-PCI II controller as in the CLANCE. In par- ticular, upon restart, the PCnet-PCI II controller reloads ...
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AMD controller, then the software must not read ahead to the next descriptor. The software should wait at a descriptor it does not own until the PCnet-PCI II controller sets OWN to ZERO to release ownership to the software. (When ...
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The following figure illustrates the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base CSR2 CSR1 IADR[31:16] IADR[15:0] Initialization Block TLE RES RLE RES PADR[31:0] PADR[47:32] RES LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0] Polling If ...
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AMD A typical receive poll is the product of the following conditions: 1. PCnet-PCI II controller does not own the current DTE and the poll time has elapsed and RXON = 1 (CSR0, bit 5 PCnet-PCI II controller ...
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PCnet-PCI II controller returns ownership for the last buffer of the first frame error occurs in the transmission before all of the bytes of the current buffer have been transferred, trans- mit status of the current buffer ...
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AMD update the current RDTE status with the end of frame (ENP) indication set, write the message byte count (MCNT) for the entire frame into RMD2 and overwrite the “current” entries in the CSRs with the “next” entries. Media Access ...
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Error Detection The MAC engine provides several facilities which report and recover from errors on the medium. In addition, it protects the network from gross errors due to inability of the host to keep pace with the MAC engine activity. ...
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AMD interFrame gap to be generated, leading to a potential reception failure of a subsequent frame. To enhance system robustness the following optional measures,as specified in 4.2.8, are recommended when InterFrame Spacing Part 1 is other than ZERO: 1. Upon ...
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If a collision is detected after 512 bit times have been transmitted, the collision is termed a late collision. The MAC Engine will abort the transmission, append the jam sequence and set the LCOL bit. No retry attempt will be ...
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AMD Preamble SFD Destination 1010....1010 10101011 Address 56 8 Bits Bits Figure 34. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame The 544 bit count is derived from the following : Minimum frame size (excluding 64 bytes 512 bits preamble/SFD, including FCS) ...
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The OWN bit(s) in the subsequent descriptor(s) will be cleared until the STP (the next frame) is found. Loss of Carrier When operating in half-duplex mode, a loss of carrier condition will be reported if the PCnet-PCI II ...
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AMD When a unicast frame arrives at the PCnet-PCI II con- troller, the controller will accept the frame if the destina- tion address field of the incoming frame exactly matches the 6-byte station address stored in the Physical Ad- dress ...
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The number of bytes to be stripped is calculated from the embedded length field (as defined in the ISO 8802-3 (IEEE/ANSI 802.3) definition) contained in the frame. The length indicates the actual number of LLC data bytes contained in the ...
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AMD Abnormal network conditions include: FCS errors Late Collision Host related receive exception conditions include MISS, BUFF, and OFLO. These are described in the section “Buffer Management Unit”. Loopback Operation Loopback is a mode of operation intended for system di- ...
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The programming of MENDECL has no effect in this mode. Miscellaneous Loopback Features All transmit and receive function programming, such as automatic transmit padding and receive pad stripping, operates identically in ...
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AMD A system that wants to stop the clock during Magic Packet mode should use one of the LED pins as an indi- cator of Magic Packet frame detection. It should also stop the clock after enabling Magic Packet mode, ...
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Cheapernet, Ethernet and IEEE-802.3. Transmitter Timing and Operation A 20 MHz fundamental mode crystal oscillator provides the basic timing reference for the MENDEC portion of the PCnet-PCI II controller. The crystal frequency is divided by two ...
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AMD interrupts the receive oscillator. The oscillator is then re- started at the second Manchester ZERO (bit time 4) and is phase locked to it result, the MENDEC acquires the clock from the incoming Manchester bit pattern in ...
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PCnet-PCI II Figure 37. AUI Differential Input Termination Collision Detection A MAU detects the collision condition on the network and generates a 10 MHz differential signal at the CI inputs. This collision signal passes through an input stage which detects ...
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AMD Multipair cables within the same outer sheath have lower crosstalk attenuation, and may allow noise emit- ted from adjacent pairs to couple into the receive pair, and be of sufficient amplitude to falsely unsquelch the T-MAU. Link Test Function ...
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These signals are in- ternal signals that can be programmed to appear on any of the LED output pins. Programming is done by writing to BCR4 to BCR7. ...
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AMD Full-Duplex Operation The PCnet-PCI II controller supports full-duplex opera- tion on all three network interfaces: AUI, 10BASE-T, and GPSI. full-duplex operation allows simultaneous trans- mit and receive activity on the TXD and RXD pairs of the 10BASE-T port, the ...
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GPSI Function GPSI I/O Type Collision I Receive Clock I Receive Data I Receive Enable I Transmit Clock I Transmit Data O Transmit Enable O Note that the XTAL1 input must always be driven with a clock source, even if ...
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AMD the EADISEL bit of BCR2 is set to ONE and the PCnet- PCI II controller is programmed to promiscuous mode (PROM bit of the Mode Register is set to ONE), then all incoming frames will be accepted, regardless of ...
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CE EROE The PCnet-PCI II controller will always read four bytes for every host Expansion ROM read access. The inter- face to the Expansion ROM runs synchronous to the PCI bus interface clock. The PCnet-PCI II controller will start the ...
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AMD The timing diagram below assumes the default pro- gramming of ROMTMG (1001b = 9 CLK). After reading the first byte, the PCnet-PCI II controller reads in three more bytes by incrementing the lower portion of the CLK 1 2 ...
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PCnet-PCI II controller from claiming any memory cycles not in- tended for it. The Expansion ROM interface uses some of the same pins as the GPSI interface. Simultaneous use of both functions is ...
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AMD controller assumes that an external pulldown device is holding the EESK/LED1/SFBD pin low indicating that there is no EEPROM in the system. Note that if the de- signer creates a system that contains an LED circuit on the EESK/LED1/SFBD ...
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EEPROM MAP The automatic EEPROM read operation will access 18 words (i.e. 36 bytes) of the EEPROM. The format of the Word Byte Address Addr. Most Significant Byte 00h 01h Second byte of the ISO 8802-3 (Lowest (IEEE/ANSI 802.3) station ...
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AMD LED and also have an EEPROM, it might be necessary to buffer the LED3 circuit from the EEPROM connection. When an LED circuit is directly connected to the EEDO/LED3/SRD pin, then it is not possible for most Microwire EEPROM ...
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Power Savings Modes The PCnet-PCI II controller supports two hardware power savings modes. Both are entered by driving the SLEEP pin LOW. The power down mode that yields the most power sav- ings is called coma mode. In coma mode, ...
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AMD Table 14. IEEE 1149.1 Supported Instruction Summary Instruction Name Instruction Code EXTEST 0000 IDCODE 0001 SAMPLE 0010 TRIBYP 0011 SETBYP 0100 BYPASS 1111 Instruction Register and Decoding Logic After the TAP FSM is reset, the IDCODE instruction is always ...
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NAND Tree Testing The PCnet-PCI II controller provides a NAND tree test mode to allow checking connectivity to the device on a printed circuit board. The NAND tree is built on all PCI bus signals. VDD RST (pin 120) INTA ...
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AMD Pin 120 (RST) is the first input to the NAND tree. Pin 117 (INTA) is the second input to the NAND tree, followed by pin 121 (CLK). All other PCI bus signals follow, counter- clockwise, with pin 57 (AD0) ...
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RST INTA CLK GNT REQ AD[31:0] FFFFFFFF C/BE[3:0] F IDSEL FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR PAR NOUT Reset There are three different types of RESET operations that may be performed on the PCnet-PCI II controller device, H_RESET, ...
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AMD terminate all network activity in an orderly sequence be- fore issuing an S_RESET. STOP A STOP reset is generated by the assertion of the STOP bit in CSR0. Writing a ONE to the STOP bit of CSR0, when the ...
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I/O Resources The PCnet-PCI II controller requires 32 bytes of address space for access to all the various internal registers as well as to some setup information stored in an external serial EEPROM. A software reset port is available, too. ...
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AMD Table 19. I/O Map In Word I/O Mode (DWIO = 0) Offset No. of Bytes Register 00h – 0Fh 16 APROM 10h 2 RDP 12h 2 RAP (shared by RDP and BDP) 14h 2 Reset Register 16h 2 BDP ...
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Table 21. I/O Map In DWord I/O Mode (DWIO = 1) Offset No. of Bytes Register 00h – 0Fh 16 APROM 10h 4 RDP 14h 4 RAP (shared by RDP and BDP) 18h 4 Reset Register 1Ch 4 BDP Table ...
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... The PCI Vendor ID register is a 16-bit register that iden- tifies the manufacturer of the PCnet-PCI II controller. Advanced Micro Devices, Inc.’s (AMD) Vendor ID is 1022h. Note that this vendor ID is not the same as the Manufacturer ID in CSR88 and CSR89. The vendor ID is assigned by the PCI Special Interest Group ...
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The PCI Device ID register is located at offset 02h in the PCI Configuration Space read only. PCI Command Register (Offset 04h) The PCI Command register is a 16-bit register used to control the gross functionality of the ...
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AMD address so that the device does not claim cycles not intended for it. MEMEN is cleared by H_RESET and is not effected by S_RESET or by setting the STOP bit. 0 IOEN I/O Space access enable. The PCnet-PCI II ...
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Parity Error Response enable bit (PCI Command register, bit 6) is set. During the data phase of all memory read commands, the PCnet-PCI II controller checks for parity error by sampling the AD[31:0] and C/BE[3:0] ...
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AMD 6–0 LAYOUT PCI configuration space layout. Read as ZEROs, write opera- tions have no effect. The layout of the PCI configuration space locations 10h to 3Ch is as shown in the table at the beginning of this section. PCI ...
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Reset regis- ter, the order of the read ac- cesses is important. 2–1 TYPE Memory type indicator. Read as ZEROs, write operations have no effect. Indicates that this base address register is 32 bits wide and ...
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AMD PCI MIN_GNT Register (Offset 3Eh) The PCI MIN_GNT register is an 8-bit register that specifies the minimum length of a burst period that the PCnet-PCI II controller needs to keep up with the net- work activity. The length of ...
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PCnet-PCI II controller when the transmitter has been on the channel longer than the time required to send the maximum length frame. BABL will be set if 1519 bytes or greater are transmitted. When BABL is set, INTA is as- ...
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AMD OWN bit in the last descriptor of a transmit frame has been cleared to indicate the frame has been sent or an error occurred in the transmission. When TINT is set, INTA is as- serted if IENA is ONE ...
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Read/Write accessible always. STOP is set by writing a ONE, by H_RESET or S_RESET. Writing a ZERO has no effect. STOP is cleared by setting either STRT or INIT. 1 STRT STRT assertion enables the PCnet-PCI II controller to send ...
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AMD CSR3: Interrupt Masks and Deferral Control Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15 RES Reserved location. Read and written as ZERO. 14 BABLM Babble Mask. If BABLM is set, the BABL ...
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While performing the search for the next STP bit that is set to ONE, the PCnet-PCI II controller will advance through the receive descriptor ring re- gardless of the state of owner- ship bits. If any of ...
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AMD and should treat the read value as undefined. 0 RES Reserved location. The default value of this bit is a ZERO. Writ- ing a ONE to this bit has no effect on device function ONE is written ...
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MFCO Missed Frame Counter Overflow is set by the PCnet-PCI II controller when Frame Counter wraps around. When MFCO is set, INTA is as- serted if IENA is ONE and the mask bit MFCOM is ZERO. Read/Write accessible always. ...
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AMD Read/Write accessible always. TXSTRTM is set to ONE by H_RESET or S_RESET and is unaffected STOP bit. 1 JAB Jabber Error is set by the PCnet- PCI II controller when the T-MAU exceeds the allowed transmis- sion time limit. ...
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SINT is cleared by H_RESET or S_RESET and is not affected by setting the STOP bit. 10 SINTE System Interrupt SINTE is set, the SINT bit will be able to set the INTR bit. Read/Write ...
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AMD Read/Write accessible always. MPEN is cleared to ZERO by H_RESET or S_RESET and is not affected by setting the STOP bit. 1 MPMODE Magic Packet Mode. Setting MPMODE to ONE will redefine the SLEEP pin magic ...
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H_RESET, S_RESET or by setting the STOP bit. CSR9: Logical Address Filter 1 Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0LADRF[31:16] Logical Address LADRF[31:16]. The content of this register is ...
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AMD Read/Write when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR15: Mode Bit Name Description This register’s fields are loaded during the PCnet-PCI II controller ...
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When LRT is cleared to ZERO, the unsquelch threshold for the RXD circuit will be the standard 10BASE-T value of 300 mV– 520 mV peak. In either case, the RXD circuit post squelch be one half of the unsquelch threshold. ...
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AMD Read/Write when either the STOP or the SPND bit is set. 3 DXMTFCS Disable Transmit CRC (FCS). When DXMTFCS is cleared to ZERO, the generate and append an FCS to the transmitted frame. When DXMTFCS is set to ONE, ...
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CRBAU Contains the upper 16 bits of the current receive buffer address at which the PCnet-PCI II controller will store incoming frame data. Read/Write when either the STOP or the SPND bit is set. These bits are unaffected by ...
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AMD S_RESET or by setting the STOP bit. CSR26: Next Receive Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NRDAL Contains the lower 16 bits of the next receive address ...
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CSR33: Next Transmit Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NXDAU Contains the upper 16 bits of the next transmit descriptor address pointer. Read/Write when either the STOP or ...
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AMD CSR40: Current Receive Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZEROs. 11–0 CRBC Current Receive Byte Count. This field is a copy ...
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CSR47: Polling Interval Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 POLLINT Polling Interval. This register contains the PCnet-PCI II controller will wait between successive polling op- erations. The POLLINT value is expressed ...
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AMD (SWSTYLE, this register). Read accessible CSRPCNET is read only. Write operations CSRPCNET will be set after H_RESET (since SWSTYLE de- faults to ZERO) and is not af- fected by S_RESET or by setting the STOP bit. 8 SSIZE32 32-Bit ...
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SWSTYLE Style [7:0] Name CSRPCNET 00h C-LANCE 1 / PCnet-ISA 01h ILACC 0 02h PCnet- 1 PCI II 03h PCnet- 1 PCI II controller All Other Reserved Undefined CSR60: Previous Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved ...
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AMD CSR64: Next Transmit Buffer Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NXBAL Contains the lower 16 bits of the next transmit buffer address from which the PCnet-PCI II controller ...
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This counter interprets the value in CSR78 as pointing to the first descriptor. A counter value of ZERO corre- sponds to the last descriptor in the ring. Read/Write when either the STOP or the SPND bit is set. ...
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AMD starts trying to transmit. When the entire frame is in the FIFO, transmission attempts will start regardless XMTSP. If the network interface is operating in half-duplex mode, regardless of XMTSP, the FIFO will not internally overwrite its data until ...
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CSR82: Bus Activity Timer Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 DMABAT Bus Activity Timer. If TIMER (CSR4, bit 13) is set to ONE, this register controls the maximum allowable time that ...
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AMD 15–12 RES Reserved locations. Read and written with ONEs. 11–0 DMABC DMA Byte Count Register. Con- tains the two’s complement of the remaining size of the current transmit or receive buffer in bytes. This register is incre- mented by ...
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ONE, and an interrupt may be gener- ated, depending upon the setting of the MERRM bit (CSR3, bit 11) and the IENA bit (CSR0, bit 6). The value in this register is inter- ...
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AMD GPSI Function GPSI I/O Type Collision I Receive Clock I Receive Data I Receive Enable I Transmit Clock I Transmit Data O Transmit Enable O 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–5 RES Reserved ...
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RAP MNEMONIC Default 0 MSRDA 0005h 1 MSWRA 0005h 2 MC 0002h 3 Reserved N/A 4 LNKST 00C0h 5 LED1 0084h 6 LED2 0088h 7 LED3 0090h 8 Reserved N/A 9 FDC 0000h 10–15 Reserved N/A 16 IOBASEL N/A 17 ...
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AMD Read/Write accessible always. TMAULOOP is cleared to ZERO by H_RESET and is unaffected by S_RESET or by setting the STOP bit. 13–9 RES Reserved locations. Written as ZEROs and read as undefined. 8 APROMWE Address PROM Write Enable. The ...
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Table 31. DXCVR Output Control Active DXCVRCTL DXCVRPOL Network Port X 0 10BASE 10BASE AUI or GPSI 1 0 AUI or GPSI 0 1 AUI or GPSI 1 1 AUI or GPSI Read/Write accessible always. DXCVRPOL ...
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AMD BCR4: Link Status LED (LNKST) Bit Name Description BCR4 determines which func- tion(s) activate the LNKST pin. The pin will indicate the logical OR of the enabled functions. BCR4 defaults to Link Status (LNKST) with pulse stretcher nabled (PSE ...
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ONE is passed to the LEDOUT signal whenever full-duplex operation on the GPSI port is enabled (FDEN bit in BCR9 is set to ONE). Read/Write accessible always. FDLSE is cleared by H_RESET and is ...
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AMD and is not affected by S_RESET or by setting the STOP bit. BCR5: LED1 Status Bit Name Description BCR5 determines which func- tion(s) activate the LED1 pin. The pin will indicate the logical OR of the enabled functions. BCR5 ...
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LEDOUT signal whenever full-duplex operation on the AUI port is enabled (both FDEN and AUIFD bits in BCR9 are set to ONE). When the GPSI port is active, a value of ONE is passed to the ...
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AMD transmission for the purpose of SQE testing will not cause the LEDOUT bit to be set. Read/Write accessible always. COLE is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. BCR6: LED2 Status ...
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LEDOUT signal whenever the Link Test Function detects a Link Pass state and the FDEN (BCR9, bit 0) bit is set. When the AUI port is active, a value of ONE is passed to the LEDOUT signal whenever full-duplex ...
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AMD within the first 4 s after every transmission for the purpose of SQE testing will not cause the LEDOUT bit to be set. Read/Write accessible always. COLE is cleared by H_RESET and is not affected by S_RESET or by ...
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LEDOUT signal whenever the Link Test Function detects a Link Pass state and the FDEN (BCR9, bit 0) bit is set. When the AUI port is active, a value of ONE is passed to the LEDOUT signal whenever full-duplex ...
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AMD inputs to the AUI or GPSI ports within the first 4 s after every transmission for the purpose of SQE testing will not cause the LEDOUT bit to be set. Read/Write accessible always. COLE is cleared by H_RESET and ...
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BCR17: I/O Base Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 IOBASEU Reserved H_RESET, the value in this register will be undefined. The setting of this register has no ef- fect ...
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AMD EXTREQ should not be set to ONE when the PCnet-PCI II controller is used in a PCI bus application. Read accessible always. Write accessible only when either the STOP or the SPND bit is set. EXTREQ H_RESET and or ...
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BCR locations will be reset to their H_RESET values. The contents of the Address PROM locations, however, be cleared. If the EEPROM detection fails, then all attempted commands will terminate early and PVALID will not be set. This applies ...
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AMD EEDET Value EEPROM (BCR19[3]) Connected EEPROM read operation is attempted. Entire read sequence will occur, checksum failure will result, PVALID is cleared to ZERO. 0 Yes EEPROM read operation is attempted. Entire read sequence will occur, checksum ...
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Table 34. Microwire Interface Pin Assignment PREAD or Auto Read in RST Pin Progress High X Low 1 Low 0 Low 0 Read accessible always. Write accessible only when either the STOP or the SPND bit is set. ESK is ...
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AMD PCnet-PCI II controller utilizes 32-bit software structures for the initialization block and the trans- mit and receive descriptor en- tries. When cleared, this bit indicates that the PCnet-PCI II controller utilizes 16-bit software structures for the initialization block and ...
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Read/Write when either the STOP or the SPND bit is set. The SWSTYLE register will contain the value 00h following H_RESET and will be unaffected by S_RESET or by setting the STOP bit. BCR21: Interrupt Control Bit Name Description 31–16 ...
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AMD Table 36. Initialization Block (SSIZE32 = 0) Address Bits 15–13 IADR+00h IADR+02h IADR+04h IADR+06h IADR+08h IADR+0Ah IADR+0Ch IADR+0Eh IADR+10h IADR+12h RLEN IADR+14h IADR+16h TLEN Table 37. Initialization Block (SSIZE32 = 1) Bits Bits Address 31–28 27–24 IADR+00h TLEN RES ...
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The values in these fields determine the number of transmit and receive Descriptor Ring Entries (DRE) which are used in the descriptor rings. Their meaning is as follows: Table 39. R/TLEN Decoding (SSIZE32 = 1) R/TLEN 0000 ...
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AMD A logical address is passed through the CRC generator, producing a 32 bit result. The high order 6 bits of the CRC is used to select one of the 64 bit positions in the Logical Address Filter. If the ...
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RMD0 Bit Name Description 31–0 RBADR Receive Buffer address. This field contains the address of the receive buffer that is associated with this descriptor. RMD1 Bit Name Description 31 OWN This bit indicates whether the descriptor entry is owned by ...
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AMD set the PCnet-PCI II controller and cleared by the host. This bit does not exist, when the PCnet-PCI II controller is pro- grammed to use 16-bit software structures for the descriptor ring entries (BCR20, SWSTYLE is cleared to ZERO). ...
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SFD de- tected, followed by 7 bytes of frame data. This requirement is unvarying, regardless of the ad- dress matching mechanisms in force at the time of reception. (I.e. physical, logical, broadcast or promiscuous). The PCnet-PCI ...
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AMD TMD0 Bit Name Description 31–0 TBADR Transmit Buffer address. This field contains the address of the transmit buffer that is associated with this descriptor. TMD1 Bit Name Description 31 OWN This bit indicates whether the descriptor entry is owned ...
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LCOL is set. The value of the ONE bit is written by the PCnet-PCI II controller. This bit has meaning only if the ENP bit is set. 26 DEF Deferred indicates PCnet-PCI II controller had to defer while trying to ...
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AMD start of a new frame and starts a new transmission. UFLO is set by the PCnet-PCI II controller and the host. 29 EXDEF Excessive Deferral. Indicates that the transmitter has experi- enced Excessive Deferral on this transmit frame, where ...
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REGISTER SUMMARY PCI Configuration Registers Offset Name 00h PCI Vendor ID 02h PCI Device ID 04h PCI Command 06h PCI Status 08h PCI Revision ID 09h PCI Programming IF 0Ah PCI Sub-Class 0Bh PCI Base-Class 0Ch Reserved 0Dh PCI Latency ...
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AMD Control and Status Registers RAP Addr Symbol Default Value 00 CSR0 uuuu 0004 01 CSR1 uuuu uuuu 02 CSR2 uuuu uuuu 03 CSR3 uuuu 0000 04 CSR4 uuuu 0115 05 CSR5 uuuu 0000 06 CSR6 uuuu uuuu 07 CSR7 ...
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Control and Status Registers (continued) RAP Addr Symbol Default Value 38 CSR38 uuuu uuuu 39 CSR39 uuuu uuuu 40 CSR40 uuuu uuuu 41 CSR41 uuuu uuuu 42 CSR42 uuuu uuuu 43 CSR43 uuuu uuuu 44 CSR44 uuuu uuuu 45 CSR45 ...
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AMD Control and Status Registers (continued) RAP Addr Symbol Default Value 83 CSR83 uuuu uuuu 84 CSR84 uuuu uuuu 85 CSR85 uuuu uuuu 86 CSR86 uuuu uuuu 87 CSR87 uuuu uuuu 88 CSR88 0242 1003 89 CSR89 uuuu 0262 90 ...
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BUS CONFIGURATION REGISTERS BCR MNEMONIC Default 0 MSRDA 0005h 1 MSWRA 0005h 2 MC 0002h 3 Reserved 4 LNKST 00C0h 5 LED1 0084h 6 LED2 0088h 7 LED3 0090h 8 Reserved 9 FDC 0000h 10–15 Reserved 16 IOBASEL 17 IOBASEU ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . Supply Voltage SSB ( ...
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DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description Crystal Input Current VILX XTAL1 Input LOW Voltage Threshold VIHX XTAL1 Input HIGH Voltage Threshold IILX XTAL1 Input LOW Current IIHX XTAL1 Input HIGH Current Power ...
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AMD DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description Twisted Pair Interface (10BASE-T) (Continued) V RXD Switching Threshold RXDTH V TXD and TXP Output HIGH Voltage TXH V TXD and TXP Output LOW Voltage ...
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SWITCHING CHARACTERISTICS: Bus Interface Parameter Symbol Parameter Description Clock Timing FCLK CLK Frequency tCYC CLK Period tHIGH CLK High Time tLOW CLK Low Time tFALL CLK Fall Time tRISE CLK Rise Time Output and Float Delay Timing tVAL AD[31:00], C/BE[3:0], ...
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AMD SWITCHING CHARACTERISTICS: Bus Interface (continued) Parameter Symbol Parameter Description EEPROM Timing fEESK (EESK) EESK Frequency tHIGH (EESK) EESK High Time tLOW EESK Low Time tVAL (EEDI) EEDI Valid Output Delay from EESK tVAL (EESK) EECS Valid Output Delay from ...
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SWITCHING CHARACTERISTICS: 10BASE-T Interface Parameter Symbol Parameter Description Transmit Timing tTETD Transmit Start of Idle tTR Transmitter Rise Time tTF Transmitter Fall Time tTM Transmitter Rise and Fall Time Mismatch tXMTON XMT Asserted Delay tXMTOFF XMT Deasserted Delay tPERLP Idle ...
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AMD SWITCHING CHARACTERISTICS: AUI Parameter Symbol Parameter Description AUI Port tDOTR DO+, DO– Rise Time (10% to 90%) tDOTF DO+, DO– Fall Time (10% to 90%) tDORM DO+, DO– Rise and Fall Time Mismatch tDOETD DO End of Transmission tPWODI ...
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SWITCHING CHARACTERISTICS: GPSI Parameter Symbol Parameter Name Transmit Timing tGPT1 TXCLK Period (802.3 Compliant) tGPT2 TXCLK HIGH Time tGPT3 TXDAT and TXEN Delay from TXCLK tGPT4 RXEN Setup Before TXCLK (Last Bit) tGPT5 RXEN Hold After tGPT6 CLSN Active Time ...
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AMD SWITCHING CHARACTERISTICS: EADI Parameter Symbol Parameter Name tEAD1 SRD Setup to SRDCLK tEAD2 SRD Hold to SRDCLK tEAD3 SF/BD Change to SRDCLK EAR Deassertion to SRDCLK (First Rising Edge) tEAD4 EAR Assertion after SFD Event (Frame Rejection) tEAD5 EAR ...
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KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS Sense Point WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from H ...
Page 184
AMD SWITCHING TEST CIRCUITS DO+ DO– TXD+ TXD– Includes Test Jig Capacitance TXP+ TXP– Includes Test Jig Capacitance 184 52.3 Test Point 154 100 ...
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SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE 2.0 V CLK 1.5 V 0.8 V 0.475 V DDB CLK 0.4 V DDB 0.325 V DDB CLK AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL, IDSEL GNT ...
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AMD SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE CLK AD[31:00] C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, DEVSEL, PERR, SERR REQ CLK AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, DEVSEL, PERR AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, DEVSEL, PERR EESK EECS 0 ...
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SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE t HIGH (EESK) EESK EEDO EECS EEDI CLK ERA EROE ERACLK ERD LOW (EESK) t VAL (EEDI,EECS) t LOW (EECS) Automatic EEPROM Read ...
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AMD SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE 2.0 V TCK 1.5 V 0.8 V JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling TCK TDI, TMS TDO Output Signals Input Signals 188 ...
Page 189
SWITCHING WAVEFORMS: 10BASE-T INTERFACE TXD+ TXP+ TXD– TXP– T XMTON XMT TXD+ TXP+ TXD- TXP- T PWLP Transmit Timing T PWPLP T PERL Idle Link Test Pulse ...
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AMD SWITCHING WAVEFORMS: 10BASE-T INTERFACE RXD RXD 190 Receive Thresholds (LRT = 1) Receive Thresholds (LRT = 0) Am79C970A V LTSQ+ V LTHS + V LTHS V LTSQ 19436A-65 ...
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SWITCHING WAVEFORMS: AUI XTAL1 t XI ISTDCLK (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ DO– DO Note 1: Internal signal and is shown for clarification only. XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note ...
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AMD SWITCHING WAVEFORMS: AUI XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Note 1: Internal signal and is shown for clarification only. Transmit Timing—End of Packet (Last Bit = 1) ...
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SWITCHING WAVEFORMS: AUI DI+/– V ASQ t PWKDI t PWODI CI+/– V ASQ t PWOCI DO+/– Receive Timing Diagram t PWKCI Collision Timing Diagram t DOETD 40 mV 100 ...
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AMD SWITCHING WAVEFORMS: GPSI (First Bit Preamble) tGPT1 tGPT2 Transmit Clock (STDCLK) tGPT3 Transmit Data (TXDAT) tGPT3 Transmit Enable (TXEN) Carrier Present (RXCRS) (Note 1) Collision (CLSN) (Note 2) Notes RXCRS is not present during transmission, LCAR bit ...
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SWITCHING WAVEFORMS: EADI Preamble SRDCLK One Zero One SRD t EAD1 t EAD2 SF/BD t EAD4 EAR Data Field SFD Bit 0 Bit 1 Bit 2 Bit 3 Bit ...
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... Copyright 1995 Advanced Micro Devices, Inc. All rights reserved. AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc. Embedded Erase and Embedded Program are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...
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PHYSICAL DIMENSIONS PQB132 Molded Carrier Ring Plastic Quad Flat Pack (measured in inches, Ring measured in millimeters) Z1 1.50 DIA. 45.87 46.13 45.50 45.90 32.15 41.37 32.25 41.63 1.097 1.103 37.87 38.13 .944 .952 35.15 35.25 1.50 DIA. 1.80 P ...
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AMD PHYSICAL DIMENSIONS PDL144 Thin Quad Flat Pack (measured in inches, Ring measured in millimeters) 144 1 1.35 1.45 1.00 REF. 198 19.80 20.20 21.80 22.20 11 – 13 ...
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APPENDIX A PCnet-PCI II Compatible Media Interface Modules PCnet-PCI II COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS The table below provides a sample list of PCnet-PCI II compatible 10BASE-T filter and transformer modules Manufacturer Part No. Bel Fuse A556-2006-DE 16-pin 0.3 DIL ...
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AMD PCnet-PCI II Compatible AUI Isolation Transformers The table below provides a sample list of PCnet-PCI II compatible AUI isolation transformers available from Manufacturer Bel Fuse A553-0506-AB Bel Fuse S553-0756-AE Halo Electronics TD01-0756K Halo Electronics TG01-0756W PCA Electronics EP9531-4 Pulse ...