DP8473V National Semiconductor, DP8473V Datasheet

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DP8473V

Manufacturer Part Number
DP8473V
Description
DP8473 Floppy Disk Controller PLUS-2
Manufacturer
National Semiconductor
Datasheet

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C 1995 National Semiconductor Corporation
DP8473 Floppy Disk Controller PLUS-2
General Description
This controller is a full featured floppy disk controller that is
software compatible with the mPD765A but also includes
many additional hardware and software enhancements
These enhancements include additional logic specifically re-
quired for an IBM PC PC-XT
This controller incorporates a precision analog data separa-
tor that includes a self trimming delay line and VCO Up to
three external filters are switched automatically depending
on the data rate selected This provides optimal perform-
ance at the standard PC data rates of 250 300 kb s and
500 kb s It also enables optimum performance at 1 Mb s
(MFM) These features combine to provide the lowest possi-
ble PLL bandwidth with the greatest lock range and hence
the widest window margin
This controller includes write precompensation circuitry A
shift register is used to provide a fixed 125 ns early-late
precompensation for all tracks at 500k 300k 250 kb s (83
ns for 1 MB s) or a precompensation value that scales with
Connection Diagrams
TRI-STATE is a registered trademark of National Semiconductor Corporation
PLUS-2
IBM
PCXT
TM
is a trademark of National Semiconductor Corporation
PCAT and PS 2 are registered trademarks of International Business Machines Corporation
Plastic Leaded Chip Carrier
See NS Package Number V52A
Order Number DP8473V
TL F 9384
PC-AT
Top View
or PS 2 design
(Continued)
Features
Y
Y
Y
Y
Y
Y
Fully mPD765A and IBM-BIOS compatible
Integrates all PCXT
Precision analog data separator
Two pin programmable precompensation modes
Other enhancements
Low power CMOS with power down mode
TL F 9384 – 1
On chip 24 MHz Crystal Oscillator
DMA enable logic
IBM compatible address decode of A0 – A2
12 mA mP bus interface buffers
48 mA floppy drive interface buffers
Data rate and drive control registers
Self-calibrating PLL and delay line
Automatically chooses one of three filters
Intelligent read algorithm
up to 1 Mb s data rate
Implied seek up to 4000 tracks
IBM or ISO formatting
TM
See NS Package Number N48A
Dual-In-Line Package
Order Number DP8473N
PCAT
Top View
and most PS 2 Logic
RRD-B30M105 Printed in U S A
TL F 9384 – 2
July 1990

Related parts for DP8473V

DP8473V Summary of contents

Page 1

... precompensation value that scales with Connection Diagrams Plastic Leaded Chip Carrier Top View Order Number DP8473V See NS Package Number V52A TRI-STATE is a registered trademark of National Semiconductor Corporation PLUS trademark of National Semiconductor Corporation ...

Page 2

General Description (Continued) the data rate 83 ns 125 ns 208 ns 250 ns for data rates 500k 300k 250 kb s respectively Specifically to support the PC-AT and PC-XT design the Floppy Disk Controller PLUS-2 includes ...

Page 3

Pin Descriptions DP8473 DP8473 Symbol PCC DIP – – 19 Address lines from the microprocessor This determines which registers the microprocessor is accessing as shown in Table IV in the Register Description Section Don’t ...

Page 4

Pin Descriptions (Continued) DP8473 DP8473 Symbol PCC DIP MTR0 8 6 This is an active low motor enable line for drive 0 which is controlled by the Drive Control register This is a high drive open drain output MTR1 7 ...

Page 5

Typical Application Recommended Plastic Chip Carrier Socket AMP P N 821551-1 or equivalent FIGURE 2 DP8473 Typical Application Functional Description This section describes the basic architectural features of the DP8473 and many of the enhancements provided Re- fer to Figure ...

Page 6

Functional Description (Continued) FIGURE 3 Block Diagram of DP8473’s Data Separator TL F 9384 – Single Data Rate Note For all filter configurations 250kb s and 300 kb s share the same filter FIGURE 4 Typical Configuration for ...

Page 7

Functional Description (Continued) the IBM standard MFM data rates To provide both FM and MFM filters external logic may be necessary The controller takes best advantage of the internal data separator by implementing a sophisticated ID search algo- rithm This ...

Page 8

Functional Description (Continued) C Filter capacitor in series with R With pump current 2 2 this determines loop bandwidth R Filter resistor Determines the PLL damping factor 2 C This filter capacitor improves the performance of the 1 PLL by ...

Page 9

Functional Description (Continued) Data Rate Register and Clock Logic This is a two bit register that controls the data rate that the controller uses See Register Description This register feeds logic that se- lects the data rates by programming a ...

Page 10

Register Description (Continued) TABLE VI Data Rate and Precompensation Programming Values DRVTYP D1 D0 Pin Normal values when PUMP ...

Page 11

Result Phase Status Registers D5 Seek End Seek or Recalibrate Command completed by the Controller (Used during Sense Interrupt com- mand ) D4 Equipment Check After a Recalibrate Command Track 0 signal failed to occur (Used during Sense Inter- rupt ...

Page 12

Result Phase Status Registers TABLE VIII Summary of FDC Registers Bits 7 6 Register DCR (W) MTR3 MTR2 Enable Enable MSR (R) Request Data for Direction Master Data 7 Data 6 DRR ( DKR (R) ...

Page 13

Processor Software Interface both be set before a byte can be read from the Data Regis- ter during the Result Phase If there is information to be transferred during the Execution Phase there are three methods that can be used ...

Page 14

Command Description Table READ DELETED DATA Command Phase MT MFM IPS DR1 DR0 Track Number Drive Head Number Sector Number Number of Bytes per Sector End of Track Sector ...

Page 15

Command Description Table SCAN HIGH OR EQUAL Command Phase MT MFM IPS DR1 DR0 Track Number Drive Head Number Sector Number Number of Bytes per Sector End of Track ...

Page 16

Command Description READ DATA The Read Data op-code is written to the data register fol- lowed by 8 bytes as specified in the Command Description Table After the last byte is written the controller starts looking for the correct sector ...

Page 17

Command Description (Continued) Data Mark is read the sector is read normally If a Regular Data Mark is found and the SK bit is set the sector is not read bit 6 of ST2 (Control Mark) is set and the ...

Page 18

Command Description (Continued) Notes e FE Data pattern of FE Clock pattern Data pattern of FC Clock pattern Data pattern of FB Clock pattern Data pattern of F8 ...

Page 19

Command Description (Continued) SEEK There are two ways to move the disk drive head to the desired track number Method One is to enable the Implied Seek Mode This way each individual Read or Write com- mand will automatically move ...

Page 20

Command Description (Continued) SENSE DRIVE STATUS This two byte command obtains the status of a disk drive Status Register 3 is returned in the result phase and con- tains the drive status This command does not generate an interrupt MODE ...

Page 21

... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( OUT Storage Temperature Range (T ) STG Package Power Dissipation ( Lead Temperature ( (Soldering 10 seconds – CCA ...

Page 22

Phase Locked Loop Characteristics Symbol Parameter V SETCUR Pin Reference REF Voltage K VCO Gain (Note 5) VCO R Recommended Pump 1 Resistor Range K Charge Pump Up Current P(UP) Gain ( (Note 6) REF P(UP) K Charge ...

Page 23

AC Electrical Characteristics MICROPROCESSOR READ TIMING Symbol Parameter t Address Valid prior to Read Strobe AR t Address Hold from Read Strobe RA t Read Strobe Width RR t Read Strobe and Chip Select to Data Valid RD t Address ...

Page 24

AC Electrical Characteristics OSC2 CLOCK AND RESET TIMING Symbol Parameter t Clock High Time H t Clock Low Time L t Reset Pulse Width RW DMA TIMING (Note 9) Symbol Parameter t End of DRQ from DAK AQ t DAK ...

Page 25

AC Electrical Characteristics DRIVE WRITE TIMING Symbol Parameter t Write Data Pulse Width WD t Head Select Setup to Write Gate Assertion HDS t Head Select Hold from Write Gate HDH Note 11 Whenever WGATE is asserted the WDATA line ...

Page 26

AC Test Conditions (Notes 11 12 13) Input Pulse Levels GND to 3V Input Rise and Fall Times Input and Output Reference Levels TRI-STATE Reference Levels Active High Active Low e Note 11 C 100 pF includes jig and scope ...

Page 27

Physical Dimensions inches (millimeters) Plastic Dual-In-Line Package (N) Order Number DP8473N NS Package Number N48A 27 ...

Page 28

... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Leaded Chip Carrier (V) Order Number DP8473V NS Package Number V52A 2 A critical component is any component of a life ...

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