MC68HC11F1VFN4 Motorola, MC68HC11F1VFN4 Datasheet
MC68HC11F1VFN4
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MC68HC11F1VFN4 Summary of contents
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...
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... Overflow (V) .............................................................................. 3-5 3.1.6.3 Zero (Z) ..................................................................................... 3-6 3.1.6.4 Negative (N) .............................................................................. 3-6 3.1.6.5 Interrupt Mask (I) ....................................................................... 3-6 3.1.6.6 Half Carry (H) ............................................................................ 3-6 3.1.6.7 X Interrupt Mask (X) .................................................................. 3-6 3.1.6.8 Stop Disable (S) ........................................................................ 3-7 MC68HC11F1 TECHNICAL DATA TABLE OF CONTENTS Title SECTION 1INTRODUCTION SECTION 2 PIN DESCRIPTIONS ) .................................. 2-6 STBY MOTOROLA Page iii ...
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... EEPROM ......................................................................................... 4-14 4.4.1.1 EEPROM Programming .......................................................... 4-14 4.4.1.2 EEPROM Bulk Erase .............................................................. 4-15 4.4.1.3 EEPROM Row Erase .............................................................. 4-15 4.4.1.4 EEPROM Byte Erase .............................................................. 4-16 4.4.2 PPROG EEPROM Programming Control Register ......................... 4-16 4.4.3 CONFIG Register Programming ..................................................... 4-17 MOTOROLA iv TABLE OF CONTENTS (Continued) Title Page MC68HC11F1 TECHNICAL DATA ...
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... Illegal Opcode Trap ......................................................................... 5-10 5.4.4 Software Interrupt ............................................................................ 5-11 5.4.5 Maskable Interrupts ......................................................................... 5-11 5.4.6 Reset and Interrupt Processing ....................................................... 5-11 5.5 Low Power Operation .............................................................................. 5-16 5.5.1 WAIT ............................................................................................... 5-17 5.5.2 STOP ............................................................................................... 5-17 SECTION 6 PARALLEL INPUT/OUTPUT 6.1 Port A ........................................................................................................ 6-1 MC68HC11F1 TECHNICAL DATA TABLE OF CONTENTS (Continued) Title Page MOTOROLA v ...
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... Serial Clock ....................................................................................... 8-4 8.3.4 Slave Select ...................................................................................... 8-4 8.4 SPI System Errors ..................................................................................... 8-4 8.5 SPI Registers ............................................................................................ 8-5 8.5.1 Serial Peripheral Control ................................................................... 8-5 8.5.2 Serial Peripheral Status ..................................................................... 8-7 8.5.3 Serial Peripheral Data Register ......................................................... 8-7 MOTOROLA vi TABLE OF CONTENTS (Continued) Title Page MC68HC11F1 TECHNICAL DATA ...
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... Conversion Sequence ..................................................................... 10-4 10.2 A/D Converter Power-Up and Clock Select ............................................. 10-5 10.3 Conversion Process ................................................................................ 10-5 10.4 Channel Assignments ............................................................................. 10-6 10.5 Single-Channel Operation ....................................................................... 10-6 10.6 Multiple-Channel Operation ..................................................................... 10-6 MC68HC11F1 TECHNICAL DATA TABLE OF CONTENTS (Continued) Title SECTION 9 TIMING SYSTEM Page MOTOROLA vii ...
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... Package Dimensions ................................................................................ B-2 B.3 Ordering Information ................................................................................ B-3 APPENDIX CDEVELOPMENT SUPPORT C.1 MC68HC11F1 Development Tools .......................................................... C-1 C.2 MC68HC11EVS — Evaluation System .................................................... C-1 C.3 M68MMDS11 — Modular Development System for M68HC11 Devices . C-1 MOTOROLA viii TABLE OF CONTENTS (Continued) Title Page MC68HC11F1 TECHNICAL DATA ...
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... WAIT Recovery from Interrupt Timing Diagram ............................................. A-8 A-6 Interrupt Timing Diagram ................................................................................ A-9 A-7 Port Read Timing Diagram ........................................................................... A-10 A-8 Port Write Timing Diagram ........................................................................... A-10 A-9 Expansion Bus Timing .................................................................................. A-13 A-10 SPI Master Timing (CPHA = 0) .................................................................... A-15 MC68HC11F1 TECHNICAL DATA LIST OF ILLUSTRATIONS Title Connections ..................................................... 4-4 STBY Page MOTOROLA ix ...
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... Figure A-11 SPI Master Timing (CPHA = 1) .................................................................... A-15 A-12 SPI Slave Timing (CPHA = 0) ...................................................................... A-16 A-13 SPI Slave Timing (CPHA = 1) ...................................................................... A-16 B-1 MC68HC11F1 68-Pin PLCC .......................................................................... B-1 B-2 MC68HC11F1 80-Pin Quad Flat Pack ........................................................... B-2 MOTOROLA x LIST OF ILLUSTRATIONS (Continued) Title Page MC68HC11F1 TECHNICAL DATA ...
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... A-3 DC Electrical Characteristics........................................................................... A-3 A-4 Control Timing ................................................................................................. A-5 A-5 Peripheral Port Timing................................................................................... A-10 A-6 Analog-To-Digital Converter Characteristics ................................................. A-11 A-7 Expansion Bus Timing................................................................................... A-12 A-8 Serial Peripheral Interface Timing ................................................................. A-14 A-9 EEPROM Characteristics .............................................................................. A-17 MC68HC11F1 TECHNICAL DATA LIST OF TABLES Title Page MOTOROLA xi ...
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... Table B-1 Device Ordering Information ........................................................................... B-3 C-1 MC68HC11F1 Development Tools .................................................................C-1 MOTOROLA xii LIST OF TABLES (Continued) Title Page MC68HC11F1 TECHNICAL DATA ...
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... Four Chip-Select Signal Outputs with Programmable Clock Stretching — Two I/O Chip Selects — One Program Chip Select — One General-Purpose Chip Select • Available in 68-Pin Plastic Leaded Chip Carrier (PLCC) and 80-Pin Plastic Quad Flat Pack (QFP) MC68HC11F1 TECHNICAL DATA INTRODUCTION MOTOROLA 1-1 ...
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... PC7 DATA7 PC6 DATA6 PC5 DATA5 PC4 DATA4 PC3 DATA3 PC2 DATA2 PC1 DATA1 PC0 DATA0 R/W Figure 1-1 MC68HC11F1 Block Diagram MOTOROLA 1-2 OSCILLATOR COP CLOCK LOGIC TIMER SYSTEM PERIODIC INTERRUPT 1024 512 BYTES BYTES RAM EEPROM CPU R/W INTRODUCTION ...
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... PG6/CSGEN 21 PG5/CSIO1 22 PG4/CSIO2 23 PG3 24 PG2 25 PG1 26 Figure 2-1 Pin Assignments for MC68HC11F1 68-Pin PLCC MC68HC11F1 TECHNICAL DATA 1 MC68HC11F1 PIN DESCRIPTIONS 60 PE4/AN4 59 PE0/AN0 58 PF0/ADDR0 57 PF1/ADDR1 56 PF2/ADDR2 55 PF3/ADDR3 54 PF4/ADDR4 53 PF5/ADDR5 52 PF6/ADDR6 51 PF7/ADDR7 PB0/ADDR8 50 49 PB1/ADDR9 48 PB2/ADDR10 PB3/ADDR11 47 46 PB4/ADDR12 45 PB5/ADDR13 44 PB6/ADDR14 MOTOROLA 2-1 ...
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... To prevent noise problems, pro- vide good power-supply bypassing at the MCU. Also, use bypass capacitors that have good high-frequency characteristics and situate them as close to the MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins are loaded. MOTOROLA 2-2 MC68HC11F1 and V ...
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... Either a crystal oscillator or a CMOS compatible clock can be used. The resulting E-clock rate is the input frequency divided by four. MC68HC11F1 TECHNICAL DATA MC34064 4.7 k MC34164 2 1 RESET GND 3 PIN DESCRIPTIONS 4 RESET RESET OF M68HC11 GND 3 MOTOROLA 2-3 ...
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... MCU Figure 2-4 Common Crystal Connections MCU Figure 2-5 External Oscillator Connections EXTAL FIRST 10M MCU XTAL * Values include all stray capacitances. Figure 2-6 One Crystal Driving Two MCUs MOTOROLA 2-4 to 100 EXTAL 10M CRYSTAL XTAL Values include all stray capacitances. ...
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... MCU will be interrupted again as soon as the interrupt mask bit in the condition code register (CCR) is cleared (normally upon return from an interrupt). Refer to SEC- TION 5 RESETS AND INTERRUPTS. MC68HC11F1 TECHNICAL DATA – 100 k OSCILLATOR LOAD CIRCUIT OR CMOS-COMPATIBLE CLOCK PIN DESCRIPTIONS EXTAL SECOND XTAL MCU when IRQ is used MOTOROLA 2-5 ...
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... F are available for I/O functions only in single-chip and bootstrap modes. The pins of ports and G are fully bidirectional. Ports B and F are output-only ports. Port input-only port. Refer to Table 2-1 for details about the 54 port signals’ func- tions within different operating modes. MOTOROLA 2-6 ) STBY ...
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... Special Test Mode PA0/IC3 PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 PB[7:0] ADDR[15:8] PC[7:0] DATA[7:0] PD0/RxD PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS PE[7:0]/AN[7:0] PF[7:0] ADDR[7:0] PG0 PG1 PG2 PG3 PG4 PG4/CSIO2 PG5 PG5/CSIO1 PG6 PG6/CSGEN PG7 PG7/CSPROG NOTE PIN DESCRIPTIONS MOTOROLA 2-7 ...
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... D is configured for general-purpose output. The DWOM control bit in the SPCR register disables port D’s P-channel output drivers. Because the N-channel driver is not affected by DWOM, setting DWOM causes port D to become an open-drain-type output port suitable for wired-OR operation. In wired- MOTOROLA 2-8 PIN DESCRIPTIONS MC68HC11F1 ...
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... N-channel nor the P-channel devices are active customary to have an external pull-up resistor on lines that are driven by open-drain devices. Port G can be configured for wired-OR operation in any operating mode. Refer to SECTION 6 PARALLEL INPUT/OUTPUT and SECTION 4 OPERATING MODES AND ON-CHIP MEMORY. MC68HC11F1 TECHNICAL DATA PIN DESCRIPTIONS MOTOROLA 2-9 ...
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... MOTOROLA 2-10 PIN DESCRIPTIONS MC68HC11F1 TECHNICAL DATA ...
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... CPU Registers M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers, discussed in the following para- graphs, are shown in Figure 3-1. MC68HC11F1 TECHNICAL DATA CENTRAL PROCESSING UNIT MOTOROLA 3-1 ...
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... A, however, there are no equivalent instructions that use B rather than A. The decimal adjust accumulator A (DAA) instruction is used after binary-coded deci- mal (BCD) arithmetic operations, but there is no equivalent BCD instruction to adjust accumulator B. MOTOROLA 3-2 7 ACCUMULATOR A 7 ...
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... Each time a new byte is pushed onto the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. At any given time, the SP holds the 16-bit address of the next free location in the stack. Figure 3 summary of SP operations. MC68HC11F1 TECHNICAL DATA CENTRAL PROCESSING UNIT MOTOROLA 3-3 ...
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... When the subroutine is finished, a return from subroutine (RTS) instruction is executed. The RTS pulls the previously stacked return address from the stack, and loads it into the program counter. Execu- tion then continues at this recovered return address. MOTOROLA 3-4 RTI, RETURN FROM INTERRUPT INTERRUPT PROGRAM ...
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... Shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 3.1.6.2 Overflow (V) The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V bit is cleared. MC68HC11F1 TECHNICAL DATA Clock Monitor $FFFE, F $FFFC, D $BFFE, F $BFFC, D CENTRAL PROCESSING UNIT COP Watchdog $FFFA, B $BFFA, B MOTOROLA 3-5 ...
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... The X interrupt mask bit is set only by hardware (RESET or XIRQ acknowledge cleared only by program instruction (TAP, where the as- sociated bit zero; or RTI, where bit 6 of the value loaded into the CCR from the stack has been cleared). There is no hardware action for clearing X. MOTOROLA 3-6 CENTRAL PROCESSING UNIT MC68HC11F1 ...
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... In the immediate addressing mode an argument is contained in the byte(s) immediate- ly following the opcode. The number of bytes following the opcode matches the size of the register or memory location being operated on. There are two-, three-, and four- MC68HC11F1 TECHNICAL DATA CENTRAL PROCESSING UNIT MOTOROLA 3-7 ...
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... Refer to Table 3-2, which shows all the M68HC11 instructions in all possible address- ing modes. For each instruction, the table shows the operand construction, the num- ber of machine code bytes, and execution time in CPU E clock cycles. MOTOROLA 3-8 CENTRAL PROCESSING UNIT MC68HC11F1 ...
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... MOTOROLA 3-9 C ...
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... M Byte CLRA Clear 0 A Accumulator A CLRB Clear 0 B Accumulator B CLV Clear Overflow 0 V Flag CMPA (opr) Compare – M Memory CMPB (opr) Compare – M Memory MOTOROLA 3-10 Addressing Instruction Mode Opcode Operand Cycles REL 2E rr REL 22 rr REL IMM DIR EXT ...
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... MOTOROLA 3- — — — — — — — — — — — — — ...
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... Right Double MUL Multiply NEG (opr) Two’s 0 – Complement Memory Byte NEGA Two’s 0 – Complement A NEGB Two’s 0 – Complement B MOTOROLA 3-12 Addressing Instruction Mode Opcode Operand Cycles INH 18 08 — EXT IND IND DIR 9D dd EXT IND IND,Y ...
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... MOTOROLA 3-13 C — — — — — — — — — — — — 1 — — — ...
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... Stack Pointer to Y TXS Transfer – Stack Pointer TYS Transfer – Stack Pointer WAI Wait for Stack Regs & WAIT Interrupt XGDX Exchange with X XGDY Exchange with Y MOTOROLA 3-14 Addressing Instruction Mode Opcode Operand Cycles B DIR EXT IND IND DIR DD dd EXT ...
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... ROM becomes present in the memory map. Reset and interrupt vectors are located in bootstrap ROM at $BFC0–$BFFF. The MCU fetches the reset vector, then executes the bootloader. MC68HC11F1 OPERATING MODES AND ON-CHIP MEMORY TECHNICAL DATA MOTOROLA 4-1 ...
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... An external pull-up resistor is required when using the SCI transmitter pin (TxD) because port D pins are configured for wired-OR operation by the bootloader. In bootstrap mode, the interrupt vectors point to RAM. This allows the use of interrupts through a jump table. Refer to Motorola application note AN1060, M68HC11 Bootstrap Mode. 4.2 On-Chip Memory The MC68HC11F1 contains 1024 bytes of on-chip RAM and 512 bytes of EEPROM ...
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... REGISTER BLOCK EXT y05F BF00 256 BYTES BOOTSTRAP ROM zD00 256 BYTES RESERVED (SPECIAL TEST MODE ONLY) zDFF zE00 512 BYTES EEPROM EXT zFFF SPECIAL TEST SPECIAL MODE BFC0 INTERRUPT BFFF VECTORS 4 5 NORMAL MODE FFC0 INTERRUPT FFFF VECTORS MOTOROLA 4-3 ...
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... The addresses shown are for default block mapping ($1000–$105F), however, the register block can be remapped to any 4-Kbyte page ($x000–$x05F) by the INIT register. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-4 . Power supply current is directly proportional to oper- ...
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... TOC3 (High) 1 Bit 0 TOC3 (Low) 9 Bit 8 TOC4 (High) 1 Bit 0 TOC4 (Low) 9 Bit 8 TI4/O5 (High) 1 Bit 0 TI4/O5 (Low) OM5 OL5 TCTL1 EDG3B EDG3A TCTL2 IC2I IC3I TMSK1 IC2F IC3F TFLG1 PR1 PR0 TMSK2 0 0 TFLG2 RTR1 RTR0 PACTL 1 Bit 0 PACNT MOTOROLA 4-5 ...
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... Registers and bits that control initialization and the basic operation of the MCU are pro- tected against writes except under special circumstances. The following table lists reg- isters that can be written only once after reset or that must be written within the first 64 cycles after reset. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-6 5 ...
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... Must be Written in Name First 64 Cycles DD Mode RBOOT Single Chip Expanded Special Bootstrap Special Test Write One Time Only Note 1 — Note 2 — No Note 4 Note 3 — No Note 5 Yes Note 6 through a pull-up resistor of voltage STBY Control Bits in HPRIO (Latched at Reset) SMOD MDA MOTOROLA 4-7 ...
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... In single-chip and bootstrap modes, IRV has no meaning or effect internal read visibility on external bus 1 = Data from internal reads is driven out the external data bus. PSEL[3:0] — Priority Select Bits [3:0] Refer to 5.3.1 Highest Priority Interrupt and Miscellaneous Register. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4 ...
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... EE[3:0] select the upper four bits of the EEPROM base address. In single-chip and bootstrap modes, EEPROM is forced to $FE00–$FFFF regardless of the value of EE[3:0]. MC68HC11F1 OPERATING MODES AND ON-CHIP MEMORY TECHNICAL DATA EE1 EE0 — NOCOP P( P(L) $103F 1 Bit 0 — EEON 1 1 Single Chip 1 1 Bootstrap 1 P Expanded 1 0 Special Test MOTOROLA 4-9 ...
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... MCU memory map. It can be written only once within the first 64 E-clock cycles after a reset. It then becomes a read-only register. INIT — RAM and I/O Mapping Register Bit 7 6 RAM3 RAM2 RESET MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-10 Table 4-4 EEPROM Mapping EEPROM Position $0E00 – $0FFF $1E00 – $1FFF $2E00 – ...
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... Bit 0 CR1* CR0 MOTOROLA 4-11 ...
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... CR[1:0] — COP Timer Rate Select Bits These control bits determine a scaling factor for the watchdog timer. Refer to SEC- TION 5 RESETS AND INTERRUPTS. 4.3.2.4 OPT2 Register The system configuration options 2 register (OPT2) controls three additional system options. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-12 MC68HC11F1 TECHNICAL DATA ...
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... BPRT[3:0] — Block Protect Bits for EEPROM 0 = Protection disabled for associated block 1 = Protection enabled for associated block MC68HC11F1 OPERATING MODES AND ON-CHIP MEMORY TECHNICAL DATA CLK4X — — — PTCON BPRT3 BPRT2 $1038 2 1 Bit 0 — — — $1035 2 1 Bit 0 BPRT1 BPRT0 MOTOROLA 4-13 ...
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... When the EELAT bit in the PPROG register is cleared, the EEPROM can be read were a ROM. The block protect register has no effect during reads. During EE- PROM programming, the ROW and BYTE bits of PPROG are not used. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-14 ...
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... Turn off high voltage and set to READ mode #$06 ERASE=1, EELAT=1, EEPGM=0 $103B Set EELAT bit $FE00 Store any data to any EEPROM address #$07 EELAT=1, EEPGM=1 $103B Turn on programming voltage DLY10 Delay 10 ms $103B Turn off high voltage and set to READ mode MOTOROLA 4-15 ...
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... Erase only one byte of EEPROM ROW — Row/All EEPROM Erase Mode (only valid when BYTE = All 512 bytes of EEPROM erased 1 = Erase only one 16-byte row of EEPROM MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-16 ROW=1, ERASE=1, EELAT=1, EEPGM=0 Set to ROW erase mode ...
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... OPERATING MODES AND ON-CHIP MEMORY TECHNICAL DATA ROW Action 0 Bulk Erase (All 512 Bytes) 1 Row Erase (16 Bytes) 0 Byte Erase 1 Byte Erase EE1 EE0 — NOCOP P( P(L) $103F 1 Bit 0 — EEON 1 1 Single Chip 1 1 Bootstrap 1 P Expanded 1 0 Special Test MOTOROLA 4-17 ...
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... Bits in the CSCTL register determine the polarity of the active state and enable both I/ O chip selects. Bits in CSGSIZ select whether each chip select is active for address- valid or E-valid time. Bits in CSSTRH select from zero to three clock cycles of delay. Refer to Figure 4-3. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-18 MC68HC11F1 ...
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... Refer to Figure 4-4. MC68HC11F1 OPERATING MODES AND ON-CHIP MEMORY TECHNICAL DATA 0000 PSIZ[A:B] = 0:0 64K PROGRAM CHIP SELECT REMAPPABLE TO 4-KBYTE BOUNDARY PSIZ[A:B] = 0:1 8000 32K PSIZ[A:B] = 1:0 C000 16K PSIZ[A:B] = 1:1 E000 8K FFFF (CSPROG) FFC0 VECTORS FFFF MOTOROLA 4-19 ...
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... IO2SA–IO2SB — I/O Chip Select 2 Clock Stretch Select Refer to Table 4-8. GSTHA–GSTHB — General-Purpose Chip Select Clock Stretch Select Refer to Table 4-8. PSTHA–PSTHB — Program Chip Select Clock Stretch Select Refer to Table 4-8. MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-20 GA15 GA[15:14] GA[15:13] ...
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... TECHNICAL DATA IO2EN IO2PL GCSPR PCSEN — PSIZB Size (Bytes GA13 GA12 GA11 GA10 $105D 2 1 Bit 0 PSIZA PSIZB 0 0 Address Range $0000–$FFFF $8000–$FFFF $C000–$FFFF $E000–$FFFF $105E 2 1 Bit 0 — — MOTOROLA 4-21 ...
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... CSGEN is valid during address valid time G1SZA–G1SZC — General-Purpose Chip Select Size Refer to Table 4-11. Table 4-11 General-Purpose Chip Select Size Control GSIZA MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-22 Size (Bytes) Valid Starting Address Bits 0 K (Disabled) None 1 K GA[15:10 GA[15:11 ...
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... CSPROG above CSGEN Set size disable — CSGEN above CSPROG 0 = CSPROG above CSGEN GAVLD in CSGSIZ — Address valid or E valid GNPOL in CSGSIZ — Active high or low GSIZA–GSIZC in CSGSIZ — Refer to Table 4–12 GA[15:10] in CSGADR GSTHA–GSTHB in CSSTRH — clocks MOTOROLA 4-23 ...
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... MOTOROLA OPERATING MODES AND ON-CHIP MEMORY 4-24 MC68HC11F1 TECHNICAL DATA ...
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... M68HC11 devices be- cause the circuit charge time constant can cause the device to misinterpret the type of reset that occurred. MC68HC11F1 TECHNICAL DATA generates a power-on reset (POR), which is used only for DD RESETS AND INTERRUPTS , the CPU cyc MOTOROLA 5-1 ...
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... Clock monitor is used as a backup for the COP system. Because the COP needs a clock to function disabled when the clocks stop. Therefore, the clock monitor sys- tem can detect clock failures not detected by the COP system. MOTOROLA 5-2 XTAL = 8.0 MHz Time- XTAL = 12 ...
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... To use STOP mode, the FCME bit must equal zero Clock monitor follows the state of the CME bit Clock monitor circuit is enabled until next reset MC68HC11F1 TECHNICAL DATA IRQE* DLY* CME FCME RESETS AND INTERRUPTS $1039 2 1 Bit 0 CR1* CR0 MOTOROLA 5-3 ...
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... Table 5-2 Reset Cause, Operating Mode, and Reset Vector Cause of Reset POR or RESET Pin Clock Monitor Failure COP Watchdog Time-out These initial states then control on-chip peripheral systems to force them to known start-up states, as follows: MOTOROLA 5-4 15 before it enters the COP watchdog system ...
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... Real-Time Interrupt (RTI) The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are masked. The rate control bits are cleared after reset and can be initialized by software before the real-time interrupt (RTI) system is used. MC68HC11F1 TECHNICAL DATA NOTE RESETS AND INTERRUPTS MOTOROLA 5-5 ...
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... Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur. Any maskable interrupt can be giv- en priority over other maskable interrupts. The first six interrupt sources are not maskable. The priority arrangement for these sources is as follows: MOTOROLA 5-6 RESETS AND INTERRUPTS MC68HC11F1 TECHNICAL DATA ...
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... Can only be written in special modes. Refer to SECTION 4 OPERAT- ING MODES AND ON-CHIP MEMORY for more information. MC68HC11F1 TECHNICAL DATA IRV PSEL3 PSEL2 RESETS AND INTERRUPTS $103C 1 Bit 0 PSEL1 PSEL0 0 1 Single Chip 0 1 Expanded 0 1 Bootstrap 0 1 Special Test MOTOROLA 5-7 ...
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... The three non-maskable interrupt sources are illegal opcode trap, software in- terrupt, and XIRQ pin. Refer to Table 5-4, which shows the interrupt sources and vec- tor assignments for each source. MOTOROLA 5-8 PSEL1 PSEL0 ...
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... RESETS AND INTERRUPTS CCR Local Mask Mask Bit — — I RIE RIE TIE TCIE ILIE I SPIE I PAII I PAOVI I TOI I I4/O5I I OC4I I OC3I I OC2I I OC1I I IC3I I IC2I I IC1I I RTII I None X None None None None None None NOCOP None CME None None MOTOROLA 5-9 ...
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... Left uninitialized, the illegal opcode vector can point to a memory location that contains an illegal opcode. This condition causes an infinite loop that causes stack underflow. The stack grows until the system crashes. MOTOROLA 5-10 CPU Registers SP SP – ...
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... CPU begins from a reset and how interrupt detection relates to normal opcode fetches. Figure 5 expansion of a block in Figure 5-1 and illustrates in- terrupt priorities. Figure 5-5 shows the resolution of interrupt sources within the SCI subsystem. MC68HC11F1 TECHNICAL DATA RESETS AND INTERRUPTS MOTOROLA 5-11 ...
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... EXTERNAL RESET DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, FFFF (VECTOR FETCH) 1A Figure 5-1 Processing Flow Out of Reset ( MOTOROLA 5-12 PRIORITY CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFC, FFFD (VECTOR FETCH) SET S, X, AND I BITS ...
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... NO NO YES SWI ? NO YES RTI ? NO EXECUTE THIS INSTRUCTION START NEXT 1A INSTRUCTION SEQUENCE RESETS AND INTERRUPTS STACK CPU REGISTERS STACK CPU REGISTERS INTERRUPT YET ? YES SET I BIT RESOLVE INTERRUPT PRIORITY AND FETCH VECTOR FOR HIGHEST PENDING SOURCE (REFER TO FIGURE 5-2) MOTOROLA 5-13 ...
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... BEGIN X BIT IN CCR SET ? NO HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = Figure 5-3 Interrupt Priority Resolution ( MOTOROLA 5-14 XIRQ PIN YES YES LOW ? NO YES YES REAL-TIME YES YES INTERRUPT ? NO TIMER YES YES IC1F ? NO TIMER YES YES IC2F ? NO TIMER YES ...
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... FETCH VECTOR TOF $FFDE, FFDF ? NO PULSE YES FETCH VECTOR ACCUMULATOR $FFDC, FFDD PAOVF ? NO PULSE YES FETCH VECTOR ACCUMULATOR $FFDA, FFDB PAIF ? NO SPIF YES FETCH VECTOR OR MODF $FFD8, FFD9 ? NO FETCH VECTOR $FFD6, FFD7 FETCH VECTOR $FFF2, FFF3 RESETS AND INTERRUPTS 2B END MOTOROLA 5-15 ...
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... Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The WAIT condition suspends processing and reduces power consumption to an interme- diate level. The STOP condition turns off all on-chip clocks and reduces power con- sumption to an absolute minimum while retaining the contents of all 1024 bytes of RAM. MOTOROLA 5-16 YES RIE = ...
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... XIRQ re- quest set to one (XIRQ masked or inhibited), then processing continues with the instruction that immediately follows the STOP instruction, and no XIRQ interrupt service is requested or pending. MC68HC11F1 TECHNICAL DATA power is maintained. The CPU DD RESETS AND INTERRUPTS MOTOROLA 5-17 ...
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... STOP, as this causes DLY to be set again by reset, im- posing the restart delay. This same delay also applies to power-on reset, regardless of the state of the DLY control bit, but does not apply to a reset while the clocks are running. MOTOROLA 5-18 RESETS AND INTERRUPTS MC68HC11F1 ...
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... PA4 PA3 PA2 OC3 OC4 IC4/OC5 IC1 OC1 OC1 OC1 — PARALLEL INPUT/OUTPUT Shared Functions Timer High-Order Address Data Bus SCI and SPI A/D Converter Low-Order Address Chip Select Outputs $1000 1 Bit 0 PA1 PA0 I I IC2 IC3 — — MOTOROLA 6-1 ...
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... Because the N-channel driver is not affected by CWOM, setting CWOM causes port C to become an open-drain-type output port suitable for wired-OR operation. In wired- OR mode, (PORTC bits are at logic level zero), pins are actively driven low by the N- channel driver. When a port C bit is at logic level one, the associated pin high- MOTOROLA 6 ...
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... I I DATA5 DATA4 DATA3 DATA2 DDC5 DDC4 DDC3 DDC2 PD5 PD4 PD3 PD2 SCK MOSI MISO PARALLEL INPUT/OUTPUT $1006 2 1 Bit 0 PC1 PC0 PC1 PC0 DATA1 DATA0 $1007 2 1 Bit 0 DDC1 DDC0 $1008 2 1 Bit 0 PD1 PD0 TxD RxD MOTOROLA 6-3 ...
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... Alt. Pin Func.: AN7 AN6 6.6 Port F Reset state is mode dependent. In single-chip or bootstrap modes, port F pins are gen- eral-purpose outputs. In expanded and test modes, port F pins are low order address outputs and PORTF is not in the memory map. MOTOROLA 6 DDD5 DDD4 DDD3 ...
Page 85
... ADDR5 ADDR4 ADDR3 ADDR2 PG5 PG4 PG3 PG2 CSIO1 CSIO2 — DDG5 DDG4 DDG3 DDG2 PARALLEL INPUT/OUTPUT $1005 2 1 Bit 0 PF1 PF0 PF1 PF0 ADDR1 ADDR0 $1002 2 1 Bit 0 PG1 PG0 — — — $1003 2 1 Bit 0 DDG1 DDG0 MOTOROLA 6-5 ...
Page 86
... Port G operates normally 1 = Port G outputs are open drain CWOM — Port C Wired-OR Mode 0 = Port C operates normally 1 = Port C outputs are open drain CLK4X — 4XOUT Clock Enable Refer to SECTION 2 PIN DESCRIPTIONS. Bits [4:0] — Not implemented Always read zero MOTOROLA 6 CLK4X — — 1 ...
Page 87
... The output of the serial shift register is applied to TxD as long as transmission is in progress or the transmit enable (TE) bit of serial communication control register 2 (SCCR2) is set. The block diagram, Figure 7-1, shows the transmit serial shift register and the buffer logic at the top of the figure. MC68HC11F1 SERIAL COMMUNICATIONS INTERFACE TECHNICAL DATA MOTOROLA 7-1 ...
Page 88
... SCDR. An advanced data recovery scheme distin- guishes valid data from noise in the serial data stream. The data input is selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity of each bit. MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-2 (WRITE-ONLY) ...
Page 89
... Figure 7-2 SCI Receiver Block Diagram MC68HC11F1 SERIAL COMMUNICATIONS INTERFACE TECHNICAL DATA 16 DATA ( RECOVERY RE M LOGIC SCSR1 SCI STATUS 1 RDRF RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 10 (11) - BIT Rx SHIFT REGISTER MSB ALL ONES RWU 8 SCDR Rx BUFFER (READ-ONLY INTERNAL DATA BUS MOTOROLA 7-3 ...
Page 90
... This type of wakeup al- lows messages to include gaps of idle time, unlike the idle-line method, but there is a loss of efficiency because of the extra bit time for each character (address bit) required for all characters. MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-4 MC68HC11F1 ...
Page 91
... The SCCR1 register provides the control bits that determine word length and select the method used for the wakeup feature. SCCR1 — SCI Control Register 1 Bit RESET MC68HC11F1 SERIAL COMMUNICATIONS INTERFACE TECHNICAL DATA R5/T5 R4/T4 R3/T3 R2/ — M WAKE — $102F 1 Bit 0 R1/T1 R0/ $102C 1 Bit 0 — — MOTOROLA 7-5 ...
Page 92
... SCI interrupt requested when IDLE status flag is set TE — Transmitter Enable When TE goes from zero to one, one unit of idle character time (logic one) is queued as a preamble Transmitter disabled 1 = Transmitter enabled RE — Receiver Enable 0 = Receiver disabled 1 = Receiver enabled MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7 RIE ILIE ...
Page 93
... The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR and then reading SCDR RxD line is active 1 = RxD line is idle MC68HC11F1 SERIAL COMMUNICATIONS INTERFACE TECHNICAL DATA RDRF IDLE $102E 2 1 Bit 0 FE — MOTOROLA 7-7 ...
Page 94
... SCP[1:0] — SCI Baud Rate Prescaler Selects Refer to the SCI baud rate generator block diagram. Table 7-1 Baud Rate Prescaler Selection Prescaler Divide Internal SCP1 SCP0 Clock MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7 SCP1 SCP0 RCKB SCR2 Crystal Frequency (MHz) 4.0 4.9152 8.0 62500 ...
Page 95
... Output from Previous Table) By 4800 19200 1 4800 19200 2 2400 9600 4 1200 4800 8 600 2400 16 300 1200 32 150 600 64 75 300 128 — 150 76800 312500 76800 312500 38400 156250 19200 78125 9600 39063 4800 19531 2400 9766 1200 4883 600 2441 MOTOROLA 7-9 ...
Page 96
... The software clearing sequence for these flags is automatic — functions that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence. MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-10 3 ...
Page 97
... The IDLE flag is set only after the RxD line has been busy and becomes idle, which prevents repeat- ed interrupts for the whole time RxD remains idle. MC68HC11F1 SERIAL COMMUNICATIONS INTERFACE TECHNICAL DATA MOTOROLA 7-11 ...
Page 98
... BEGIN YES RDRF = YES YES TDRE = YES YES IDLE = – VALID SCI REQUEST Figure 7-4 Interrupt Source Resolution Within SCI MOTOROLA SERIAL COMMUNICATIONS INTERFACE 7-12 YES RIE = YES TIE = YES TCIE = YES ILIE = YES YES YES YES – VALID SCI REQUEST ...
Page 99
... SPI status register (SPSR). The SPI control block rep- resents those functions that control the SPI system through the serial peripheral con- trol register (SPCR). Refer to Figure 8-1, which shows the SPI block diagram. MC68HC11F1 TECHNICAL DATA SERIAL PERIPHERAL INTERFACE MOTOROLA 8-1 ...
Page 100
... A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities master SPI device, the select line can optionally be used to indicate a multiple master bus contention. Refer to Figure 8-2. MOTOROLA 8-2 MSB LSB ...
Page 101
... All SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register. MC68HC11F1 TECHNICAL DATA SLAVE CPHA = 1 TRANSFER IN PROGRESS MASTER TRANSFER IN PROGRESS SLAVE CPHA = 0 TRANSFER IN PROGRESS SERIAL PERIPHERAL INTERFACE LSB 2 1 LSB 4 5 MOTOROLA 8-3 ...
Page 102
... SPI device simultaneously tries master. This error is called a mode fault. The second type of error, write collision, indicates that an attempt was made to write data to the SPDR while a transfer was in progress. MOTOROLA 8-4 SERIAL PERIPHERAL INTERFACE MC68HC11F1 ...
Page 103
... Refer to the following information for a description of how these reg- isters are organized. 8.5.1 Serial Peripheral Control SPCR — Serial Peripheral Control Register Bit 7 6 SPIE SPE RESET MC68HC11F1 TECHNICAL DATA DWOM MSTR CPOL CPHA SERIAL PERIPHERAL INTERFACE $1028 2 1 Bit 0 SPR1 SPR0 MOTOROLA 8-5 ...
Page 104
... When the device is configured as slave, these bits have no effect. Refer to Table 8-1. E Clock SPR[1:0] Divide MOTOROLA 8-6 Table 8-1 SPI Clock Rates Frequency at Frequency MHz MHz 1.0 MHz 1.5 MHz 500 kHz 750 kHz 125 kHz 187.5 kHz 62.5 kHz 93 ...
Page 105
... SPDR — SPI Data Register Bit 7 6 Bit 7 6 SPI is double buffered in and single buffered out. MC68HC11F1 TECHNICAL DATA — MODF — — SERIAL PERIPHERAL INTERFACE $1029 2 1 Bit 0 — — $102A 2 1 Bit Bit 0 MOTOROLA 8-7 ...
Page 106
... MOTOROLA 8-8 SERIAL PERIPHERAL INTERFACE MC68HC11F1 TECHNICAL DATA ...
Page 107
... If the COP is allowed to time out, a reset is generated, which drives the RESET pin low to reset the MCU and the external system. Refer to Table 9-1 for crystal related frequencies and periods. MC68HC11F1 TECHNICAL DATA tapped off of the free-running counter TIMING SYSTEM MOTOROLA 9-1 ...
Page 108
... OSCILLATOR AND CLOCK GENERATOR (DIVIDE BY FOUR) PRESCALER ( 2, 4, 16, 32) SPR[1:0] PRESCALER ( 13) SCP[1: PRESCALER ( 16) PR[1:0] TCNT IC/OC Figure 9-1 Timer Clock Divider Chains MOTOROLA 9-2 PRESCALER ( 1, 2, 4,....128) SCR[2:0] PRESCALER ( RTR[1: PRESCALER ( 1, 4, 16, 64) CR[1:0] TOF FF1 CLEAR COP SYSTEM TIMER RESET ...
Page 109
... Main Timer Count Rates 500 ns 333 ns 32.768 ms 21.845 ms 2.0 s 1.333 s 131.07 ms 87.381 ms 4.0 s 2.667 s 262.14 ms 174.76 ms 8.0 s 5.333 s 524.29 ms 349.52 ms TIMING SYSTEM 16.0 MHz Other Rates 4.0 MHz (E) 250 ns (1/E) 250 ns (1/E) 16.384 /E) 1.0 s (4/E) 65.536 /E) 2.0 s (8/E) 131. /E) 4.0 s (16/E) 262. /E) MOTOROLA 9-3 ...
Page 110
... I4/O5 16-BIT LATCH CLK TIC1 (HI) TIC1 (LO) 16-BIT LATCH CLK TIC2 (HI) TIC2 (LO) 16-BIT LATCH CLK TIC3 (HI) TIC3 (LO) Figure 9-2 Capture/Compare Block Diagram MOTOROLA 9-4 TCNT (HI) TCNT (LO) TOI 16-BIT FREE-RUNNING TOF COUNTER TAPS FOR RTI, COP WATCHDOG AND PULSE ACCUMULATOR TMSK1 OC1I TFLG1 ...
Page 111
... IC4 func- tions only if the I4/O5 bit in the PACTL register is set. Refer to Table 9-2 for timer con- trol configuration. MC68HC11F1 TECHNICAL DATA EDG1B EDG1A EDG2B EDG2A TIMING SYSTEM $1021 2 1 Bit 0 EDG3B EDG3A MOTOROLA 9-5 ...
Page 112
... The value in the compare register is compared to the value of the free-running counter on every bus cycle. When the compare register matches the counter value, an output compare status flag is set. The flag can be used to initiate the automatic actions for that output compare function. MOTOROLA 9 ...
Page 113
... However, if coherency is not needed, byte accesses can be used. For output compare functions, write a comparison value to output compare registers TOC1–TOC4 and TI4/O5. When TCNT value matches the comparison value, speci- fied pin actions occur. MC68HC11F1 TECHNICAL DATA TIMING SYSTEM MOTOROLA 9-7 ...
Page 114
... Not affected 1 = Output x action occurs Bits [2:0] — Not implemented Always read zero 9.3.3 Output Compare Mask Registers Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits of the OC1M register correspond to PA[7:3]. MOTOROLA 9 ...
Page 115
... The bits of this register specify the action taken as a result of a successful OCx com- pare. MC68HC11F1 TECHNICAL DATA OC1M5 OC1M4 OC1M3 OC1D5 OC1D4 OC1D3 TIMING SYSTEM $100C 2 1 Bit 0 — — — $100D 2 1 Bit 0 — — — $100E, $100F 9 Bit 8 TCNT (High) 1 Bit 0 TCNT (Low) MOTOROLA 9-9 ...
Page 116
... I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit. IC1I–IC3I — Input Capture x Interrupt Enable If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the corresponding interrupt sources. MOTOROLA 9- ...
Page 117
... Refer to Table 9-1 and Table 9-4 for specific timing values. MC68HC11F1 TECHNICAL DATA OC3F OC4F I4/O5F IC1F PAOVI PAII — — TIMING SYSTEM $1023 2 1 Bit 0 IC2F IC3F $1024 2 1 Bit 0 PR1 PR0 MOTOROLA 9-11 ...
Page 118
... The RTII bit in the TMSK2 register enables the interrupt capability. The four different rates available are a product of the MCU oscil- lator frequency and the value of bits RTR[1:0]. Refer to Table 9-4, which shows the periodic real-time interrupt rates. MOTOROLA 9-12 Prescaler 0 0 ...
Page 119
... TMSK2 enable the corresponding interrupt sources. MC68HC11F1 TECHNICAL DATA Table 9-4 RTI Rate Selection MHz MHz 4.096 ms 2.731 ms 8.192 ms 5.461 ms 16.384 ms 10.923 ms 32.768 ms 21.845 PAOVI PAII — — NOTE TIMING SYSTEM MHz MHz 2.048 /E) 4.096 /E) 8.192 /E) 16.384 /E) $1024 2 1 Bit 0 PR1 PR0 MOTOROLA 9-13 ...
Page 120
... PACTL — Pulse Accumulator Control Bit 7 6 — PAEN RESET Bit 7 — Not implemented Always reads zero PAEN — Pulse Accumulator System Enable Refer to 9.6 Pulse Accumulator. PAMOD — Pulse Accumulator Mode Refer to 9.6 Pulse Accumulator. MOTOROLA 9- PAOVF PAIF — PAMOD PEDGE — ...
Page 121
... In gated time accumulation mode, a free-running E-clock signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer to Table 9-6. The pulse accumulator counter can be read or written at any time. MC68HC11F1 TECHNICAL DATA 13 rate clock that is compensated in- TIMING SYSTEM 64 MOTOROLA 9-15 ...
Page 122
... Pulse Accumulator Control Register Four of this register's bits control an 8-bit pulse accumulator system. Another bit en- ables either the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt system. MOTOROLA 9-16 PAI EDGE PAEN ...
Page 123
... TECHNICAL DATA PAMOD PEDGE — I4/ PEDGE Action on Clock 0 PAI falling edge increments the counter. 1 PAI rising edge increments the counter zero on PAI inhibits counting one on PAI inhibits counting TIMING SYSTEM $1026 2 1 Bit 0 RTR1 RTR0 $1027 2 1 Bit Bit 0 MOTOROLA 9-17 ...
Page 124
... In this mode, the PAIF bit must be polled by user software to determine when an edge has occurred. When the PAII control bit is set, a hardware interrupt request is generated each time PAIF is set. Before leaving the interrupt service routine, software must clear PAIF by writing to the TFLG2 register. MOTOROLA 9- ...
Page 125
... The multiplexer selects one of 16 inputs for conversion. Input selection is controlled by the value of bits CD–CA in the ADCTL register. The eight port E pins are fixed-direc- tion analog inputs to the multiplexer, and internal analog signal lines are routed to it. MC68HC11F1 TECHNICAL DATA ANALOG-TO-DIGITAL CONVERTER pin is DD MOTOROLA 10-1 ...
Page 126
... N-channel input gate is on. Because no P-channel devices are directly connect either input pins or reference voltage pins, voltages above V latchup problem, although current should be limited according to maximum ratings. Refer to Figure 10-2, which is a functional diagram of an input pin. MOTOROLA 10-2 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD ...
Page 127
... Four 8-bit registers (ADR1–ADR4) store conversion results. Each of these registers can be accessed by the processor in the CPU. The conversion complete flag (CCF) MC68HC11F1 TECHNICAL DATA DIFFUSION AND POLY COUPLER 400 nA – ~ 0.7 V JUNCTION LEAKAGE ANALOG-TO-DIGITAL CONVERTER * ~ 20 pF DAC CAPACITANCE V RL and AV pins MOTOROLA 10-3 ...
Page 128
... Synchronization is referenced to the system E clock. E CLOCK WRITE 12 E CYCLES TO ADCTL SAMPLE ANALOG INPUT CONVERT FIRST CHANNEL AND UPDATE ADDR1 AND UPDATE ADDR2 0 32 Figure 10-3 A/D Conversion Sequence MOTOROLA 10-4 MSB BIT 6 BIT 5 BIT CYCLES CYC CYC CYC SUCCESSIVE APPROXIMATION SEQUENCE ...
Page 129
... For ratiometric conversions of this type, the source of each analog input should use V referenced MC68HC11F1 TECHNICAL DATA IRQE* DLY* CME FCME converts to $00 and an input voltage equal ANALOG-TO-DIGITAL CONVERTER $1039 2 1 Bit 0 CR1* CR0 con the supply voltage and be MOTOROLA 10-5 ...
Page 130
... SCAN = 1, conversions continue to be performed on the selected group of channels with the fifth conversion being stored in register ADR1 (replacing the earlier conversion result for the first channel in the group), the sixth conversion overwriting ADR2, and so on. MOTOROLA 10-6 Channel Result in ADRx if ...
Page 131
... CD– CA (bits [3:0] of the ADCTL register). When this bit is set, the A/D system is configured to perform a conversion on each of four channels where each result register corre- sponds to one channel. MC68HC11F1 TECHNICAL DATA SCAN MULT ANALOG-TO-DIGITAL CONVERTER $1030 2 1 Bit MOTOROLA 10-7 ...
Page 132
... Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register is set, indicating a conversion sequence is complete. If conversion results are needed sooner, refer to Figure 10-3, which shows the A/D conversion se- quence diagram. MOTOROLA 10-8 NOTE Channel Signal ...
Page 133
... ADR1–ADR4 — A/D Results $1031 Bit 7 6 $1032 Bit 7 6 $1033 Bit 7 6 $1034 Bit 7 6 MC68HC11F1 TECHNICAL DATA ANALOG-TO-DIGITAL CONVERTER $1031–$1034 2 1 Bit 0 ADR1 2 1 Bit 0 ADR2 2 1 Bit 0 ADR3 2 1 Bit 0 ADR4 MOTOROLA 10-9 ...
Page 134
... MOTOROLA 10-10 ANALOG-TO-DIGITAL CONVERTER MC68HC11F1 TECHNICAL DATA ...
Page 135
... Tying unused inputs to an appropriate logic voltage level (either GND or V operation. MC68HC11F1 TECHNICAL DATA Table A-1 Maximum Ratings Symbol stg ELECTRICAL CHARACTERISTICS Value Unit – 0 7.0 V – – – 105 – 125 – 150 enhances reliability of DD MOTOROLA A-1 ...
Page 136
... Total Power Dissipation Device Internal Power Dissipation I/O Pin Power Dissipation A Constant NOTES: 1 This is an approximate value, neglecting P 2. For most applications P « constant pertaining to the device. Solve for K with a known T this value solve for P D MOTOROLA A-2 Symbol (Note ...
Page 137
... ELECTRICAL CHARACTERISTICS Min Max Unit — 0 – 0.1 — – 0.8 — — 0 – 0.3 0 — — — 100 500 A 4 — — — — — 200 pF — MHz 3 MHz 4 MHz Unit 149 209 275 mW specification OH MOTOROLA A-3 ...
Page 138
... INPUTS ~V DD OUTPUTS ~ TESTING NOTES: 1. Full test loads are applied during all DC electrical tests and AC timing measurements. 2. During AC timing measurements, inputs are driven to 0.4 volts and V taken at the 20% and 70 points. MOTOROLA A-4 0 NOM NOMINAL TIMING V DD – 0.8 V 0.4 V ...
Page 139
... MHz 8.0 dc 12.0 dc 16.0 MHz — 133 — 113 — ns — 16 — 16 — t — 1 — 1 — t — 2 — 2 — t — 10 — 10 — ns — 353 — 270 — — 4 — — 353 — 270 — ns MOTOROLA cyc cyc cyc cyc A-5 ...
Page 140
... Figure A-3 POR External Reset Timing Diagram MOTOROLA A-6 ELECTRICAL CHARACTERISTICS MC68HC11F1 TECHNICAL DATA ...
Page 141
... Figure A-4 STOP Recovery Timing Diagram MC68HC11F1 TECHNICAL DATA ELECTRICAL CHARACTERISTICS MOTOROLA A-7 ...
Page 142
... Figure A-5 WAIT Recovery from Interrupt Timing Diagram MOTOROLA A-8 ELECTRICAL CHARACTERISTICS MC68HC11F1 TECHNICAL DATA ...
Page 143
... Figure A-6 Interrupt Timing Diagram MC68HC11F1 TECHNICAL DATA ELECTRICAL CHARACTERISTICS MOTOROLA A-9 ...
Page 144
... Ports C, D, and G timing is valid for active drive (CWOM, DWOM, and GWOM bits cleared). 2. All timing is shown with respect to 20 PORTS PORTS Figure A-7 Port Read Timing Diagram E PORTS PREVIOUS PORT DATA PORTS Figure A-8 Port Write Timing Diagram MOTOROLA A-10 = 5.0 Vdc 5 Vdc Symbol 2.0 MHz ...
Page 145
... Guaranteed — — — — — — — — — (Typ) — — — — 400 400 400 — 1.0 1.0 1.0 2 MHz, source impedances 10% R MOTOROLA Bits LSB LSB LSB LSB LSB LSB cyc s Hex Hex t cyc A-11 ...
Page 146
... Address Valid to Chip Select Time 57 Address Valid to Data Three-State Time NOTES: 1. Input clocks with duty cycles other than 50% affect bus performance. 2. Indicates a parameter affected by clock stretching. Add n depending on values written to CSSTRH register. 3. All timing is shown with respect to 20% V MOTOROLA A- 5.0 Vdc 5 Vdc ...
Page 147
... E 11 R/W, ADDRESS READ DATA WRITE DATA CS E VALID CS AD VALID 54 Figure A-9 Expansion Bus Timing MC68HC11F1 TECHNICAL DATA ELECTRICAL CHARACTERISTICS MOTOROLA A-13 ...
Page 148
... SPI Inputs (SCK, MOSI, MISO, and SS) 13 Fall Time (70 20 SPI Outputs (SCK, MOSI, and MISO) SPI Inputs (SCK, MOSI, MISO, and SS) NOTES: 1. All timing is shown with respect to 20 Signal production depends on software. 3. Assumes 200 pF load on all SPI pins. MOTOROLA A- 5.0 Vdc 5 Vdc Symbol 2.0 MHz ...
Page 149
... Figure A-11 SPI Master Timing (CPHA = 1) MC68HC11F1 TECHNICAL DATA MSB IN BIT MASTER MSB OUT BIT MSB IN BIT MASTER MSB OUT BIT ELECTRICAL CHARACTERISTICS 12 12 LSB IN 11 (ref) MASTER LSB OUT 12 12 SEE NOTE 13 SEE NOTE 6 7 LSB IN 11 (ref) MASTER LSB OUT 12 MOTOROLA A-15 ...
Page 150
... Figure A-12 SPI Slave Timing (CPHA = 0) SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO SEE SLAVE NOTE (OUTPUT) MOSI (INPUT) NOTE: Not defined but normally LSB of character previously transmitted. Figure A-13 SPI Slave Timing (CPHA = 1) MOTOROLA A- MSB OUT BIT BIT ...
Page 151
... Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information. MC68HC11F1 TECHNICAL DATA = 5.0 Vdc 10 Vdc Temperature Range 0 to 70, – –40 to 105 10 20 Must use RCO 10 10 10,000 10,000 10 ELECTRICAL CHARACTERISTICS Unit –40 to 125 Must use RCO 10,000 Cycles 10 10 Years MOTOROLA A-17 ...
Page 152
... MOTOROLA A-18 ELECTRICAL CHARACTERISTICS MC68HC11F1 TECHNICAL DATA ...
Page 153
... RESET 17 XIRQ 18 IRQ 19 PG7/CSPROG 20 PG6/CSGEN 21 PG5/CSIO1 22 PG4/CSIO2 23 PG3 24 PG2 25 PG1 26 Figure B-1 MC68HC11F1 68-Pin PLCC MC68HC11F1 TECHNICAL DATA 60 PE4/AN4 1 59 PE0/AN0 58 PF0/ADDR0 57 PF1/ADDR1 56 PF2/ADDR2 55 PF3/ADDR3 54 PF4/ADDR4 53 PF5/ADDR5 MC68HC11F1 52 PF6/ADDR6 51 PF7/ADDR7 50 PB0/ADDR8 PB1/ADDR9 49 48 PB2/ADDR10 47 PB3/ADDR11 PB4/ADDR12 46 45 PB5/ADDR13 44 PB6/ADDR14 MOTOROLA B-1 ...
Page 154
... PB2/ADDR10 7 PB1/ADDR9 8 PB0/ADDR8 9 PF7/ADDR7 10 PF6/ADDR6 11 PF5/ADDR5 12 PF4/ADDR4 13 PF3/ADDR3 14 PF2/ADDR2 15 PF1/ADDR1 16 PF0/ADDR0 17 PE0/AN0 18 PE4/AN4 Figure B-2 MC68HC11F1 80-Pin Quad Flat Pack B.2 Package Dimensions For case outlines please visit our website at http://design-net.sps.mot.com. MOTOROLA B MC68HC11F1 PG1 PG2 PG3 PG4/CSIO2 PG5/CSIO1 PG6/CSGEN PG7/CSPROG ...
Page 155
... C – 125 C Frequency MC Order Number 2 MHz MC68HC11F1CPU2 3 MHz MC68HC11F1CPU3 4 MHz MC68HC11F1CPU4 2 MHz MC68HC11F1VPU2 3 MHz MC68HC11F1VPU3 4 MHz MC68HC11F1VPU4 2 MHz MC68HC11F1MPU2 3 MHz MC68HC11F1MPU3 2 MHz MC68HC11F1CFN2 3 MHz MC68HC11F1CFN3 4 MHz MC68HC11F1CFN4 2 MHz MC68HC11F1VFN2 3 MHz MC68HC11F1VFN3 4 MHz MC68HC11F1VFN4 2 MHz MC68HC11F1MFN2 3 MHz MC68HC11F1MFN3 MOTOROLA B-3 ...
Page 156
... MOTOROLA B-4 MC68HC11F1 TECHNICAL DATA ...
Page 157
... Logic analyzer connector C.3 M68MMDS11 — Modular Development System for M68HC11 Devices The M68MMDS11 Motorola Modular Development System (MMDS11 tool for de- veloping embedded systems based on M68HC11 MCUs. The MMDS11 is an emulator system that provides an on-screen bus state analyzer and real-time memory monitor- ing windows ...
Page 158
... RS-232 operation speeds as high as 57.6 Kbaud • On-screen, context-sensitive help • Mouse or keyboard control of software • Built-in power supply • Compact size: 15.38 inches (390.6 mm) deep, 10.19 inches (258.83 mm) wide, and 2.75 inches (69.85 mm) high. Station module weighs 6.0 pounds (2.72 kg). MOTOROLA C-2 MC68HC11F1 TECHNICAL DATA ...