PLS153N Philips Semiconductors, PLS153N Datasheet
PLS153N
Available stocks
Related parts for PLS153N
PLS153N Summary of contents
Page 1
... PLS153: 40ns (max) – PLS153A: 30ns (max) Input loading: –100 A (max) Power dissipation: 650mW (typ) 3-State outputs TTL compatible APPLICATIONS Random logic Code converters Fault detectors Function generators Address mapping Multiplexing ORDER CODE PLS153N, PLS153AN PLS153A, PLS153AA 1 Product specification PLS153/A PIN CONFIGURATIONS N Package ...
Page 2
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) LOGIC DIAGRAM (LOGIC TERMS– NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. October 22, 1993 ...
Page 3
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER V Supply voltage CC V Input voltage IN V Output voltage OUT I Input currents IN I Output currents OUT T Operating temperature range amb T Storage temperature range stg NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only ...
Page 4
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) LOGIC FUNCTION TYPICAL PRODUCT TERM TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY = OUTPUT POLARITY = NOTES: 1. For each of the 10 outputs, either function Z (Active-High (Active-Low) is available, but not both. The desired output polarity is programmed via the Ex-OR gates. ...
Page 5
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) AC ELECTRICAL CHARACTERISTICS +75 C, 4.75V V 5.25V, R amb CC 1 SYMBOL PARAMETER FROM t Propagation delay Input Output enable Input Output disable Input OD NOTES: 1. All typical values are 5V + amb 2. For 3-State output; output enable times are tested with C closed for high-impedance to Low tests ...
Page 6
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) TIMING DIAGRAM I, B 1. LOGIC PROGRAMMING The PLS153/A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP, Data I/O’s ABEL and Logical Devices, Inc. CUPL design software packages ...
Page 7
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) OR ARRAY – ( STATUS CODE ACTIVE NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate P will be unconditionally inhibited n if both the True and Complement of an input (either are left intact. VIRGIN STATE ...
Page 8
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) PROGRAM TABLE PIN 8 October 22, 1993 AND B( Product specification PLS153/A POLARITY OR B( SP00283 ...
Page 9
... Philips Semiconductors Programmable Logic Devices Programmable logic arrays (18 42 10) SNAP RESOURCE SUMMARY DESIGNATIONS P 31 DIN153 I0 NIN153 October 22, 1993 DIN153 NIN153 AND CAND EXOR153 9 Product specification PLS153/A TOUT153 B9 B0 SP00284 ...