LTC4251IS6#PBF Linear Technology, LTC4251IS6#PBF Datasheet - Page 18
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LTC4251IS6#PBF
Manufacturer Part Number
LTC4251IS6#PBF
Description
Manufacturer
Linear Technology
Datasheet
1.LTC4251IS6PBF.pdf
(24 pages)
Specifications of LTC4251IS6#PBF
Lead Free Status / Rohs Status
Compliant
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APPLICATIONS INFORMATION
LTC4251/LTC4251-1/
LTC4251-2
Analog Current Limit and Fast Current Limit
In Figure 13a, when SENSE exceeds V
by the analog current limit amplifier loop. When SENSE
drops below V
13b, when a severe fault occurs, SENSE exceeds V
and GATE immediately pulls down until the analog current
amplifier can establish control. If TIMER reaches V
GATE pulls low and latches off.
Resetting a Fault Latch
As shown in Figure 14, a latched fault is reset by either
pulling UV/OV below V
18
SENSE
TIMER
UV/0V
GATE
ACL
V
, GATE is allowed to pull up. In Figure
UVLO
UVLO
1
V
Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to V
UV/0V
or pulling TIMER below V
2
V
V
DROPS BELOW V
UV/0V
UVHI
CLEARS V
ACL
INITIAL TIMING CYCLE
, GATE is regulated
UVHI
UVLO
5.8µA
, CHECK TIMER < V
. TIMER, GATE, AND SENSE ARE PULLED TO V
TMRH
TMRL
FCL
V
TMRH
TMRL
,
.
V
, GATE < V
TMRL
An initial timing cycle is initiated if UV/OV is used for reset.
If TIMER is used for reset, the initial timing cycle is skipped.
Internal Soft-Start
An internal soft-start feature ramps the positive input of
the analog current limit amplifier during initial start-up.
The ramp duration is approximately 200µs. This feature
reduces load current dl/dt at start-up. As illustrated in
Figure 15, soft-start is initiated by a TIMER transition from
V
threshold after an OV fault. After soft-start duration, load
current is limited by V
TMRH
3
58µA
GATEL
4
START-UP CYCLE
TIMER CLEARS V
5 6
to V
230µA
AND SENSE < V
TMRL
EE
7 8 9
.
58µA
TMRL
V
V
or when UV/OV falls below the V
CB
ACL
CB
.
, CHECK GATE < V
ACL
5.8µA
/R
S
.
EE
)
GATEL
AND SENSE < V
5.8µA
425112 F09
CB
.
425112fb
OVLO