LM4946SQ/NOPB National Semiconductor, LM4946SQ/NOPB Datasheet - Page 23

• Manufacturer Part Number: LM4946SQ/NOPB
• Description: IC AUDIO SUBSYSTEM 1.3W D 24LLP
• Manufacturer: National Semiconductor
• Series: Boomer®r
• Type: Class Dr

Specifications of LM4946SQ/NOPB

• Output Type: 1-Channel (Mono) with Stereo Headphones
• Max Output Power X Channels @ Load: 1.3W x 1 @ 8 Ohm; 85mW x 2 @ 32 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: 3D, Depop, I²C, Mute, Shutdown, SPI, Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 24-LLP
• For Use With: LM4946SQEVAL - BOARD EVALUATION LM4946SQ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM4946SQ; LM4946SQTR

EC — Externally Controlled
1. Bits MVC0 — MVC4 control 32 step volume control for MONO input
2. Bits LVC0 — LVC4 control 32 step volume control for LEFT input
3. Bits RVC0 — RVC4 control 32 step volume control for RIGHT input
4. Bits MC0 — MC2 control 8 distinct modes
5. Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function
6. N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0), and N3D1 = 0 provides a “wider” aural effect or N3D1 = 1 a “narrower” aural effect
7. Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0
On initial POWER ON, the default mode is 000
P = Phone-in (Mono)
R = R
L = L
SD = Shutdown
MUTE = Mute Mode
G
G
G
Mono Volume Control
Right Volume Control
Output Mode
Left Volume Control
P
R
L
ID_ENB = 0
ID_ENB = 1
Programmable 3D
= Left stereo volume control gain
= Phone In (Mono) volume control gain
= Right stereo volume control gain
Number
Address
IN
Mode Control
IN
Chip
0
1
2
3
4
5
6
7
MC2
0
0
0
0
1
1
1
1
A7
1
1
1
Maximum
Medium
D7
0
0
1
1
1
High
Low
MC1
0
0
1
1
0
0
1
1
A6
D6
1
1
1
0
1
0
1
1
MC0
TABLE 3. Programmable National 3D Audio
0
1
0
1
0
1
0
1
D5
0
0
0
0
1
TABLE 4. Output Mode Selection
A5
TABLE 2. Control Registers
2 X (G
1
1
1
2 X (G
2 X (G
TABLE 1. Chip Address
Handsfree Speaker
MVC4
RVC4
LVC4
L
L
R
D4
X L + G
G
G
0
0
Output
X L + G
X R + G
P
P
SD
SD
SD
SD
X P
X P
A4
23
1
1
1
R
R
L
X R) +
X R)
X L)
MVC3
RVC3
N3D3
LVC3
OCL
D3
N3D3
0
0
1
1
A3
1
1
1
G
Right HP Output
R
X R + G
G
G
G
MUTE
MUTE
MUTE
P
R
R
MVC2
RVC2
SD
N3D2
LVC2
MC2
X P/2
D2
X R
X R
P
A2
0
0
0
X P/2
MVC1
RVC1
N3D1
LVC1
MC1
D1
EC
A1
0
1
G
Left HP Output
L
X L + G
N3D2
G
G
G
0
1
0
1
MUTE
MUTE
MUTE
P
L
L
SD
X P/2
X L
X L
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P
MVC0
N3D0
RVC0
LVC0
X P/2
MC0
A0
D0
0
0
0