FW802B-DB LSI, FW802B-DB Datasheet - Page 22

• Manufacturer Part Number: FW802B-DB
• Manufacturer: LSI

Specifications of FW802B-DB

• Lead Free Status / Rohs Status: Not Compliant

FW802B Low-Power PHY IEEE 1394A-2000
Two-Cable Transceiver/Arbiter Device
Internal Register Configuration
Table 9. PHY Register Fields for the Cable Environment (continued)
The port status page is used to access configuration and status information for each of the PHY’s ports. The port is
selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address
0111
meanings of the register fields with the port status page are defined by Table 11.
Table 10. PHY Register Page 0: Port Status Page
22
22
Page_select
Enab_accel
Enab_multi
Port_select
Address
1000
1001
1010
1011
1100
1101
1110
1111
Field
2
. The format of the port status page is illustrated by Table 10 below; reserved fields are shown shaded. The
2
2
2
2
2
2
2
2
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Size Type
1
1
3
4
Bit 0
Negotiated_speed
AStat
rw
rw
rw
rw
REQUIRED
Power Reset
Bit 1
Value
000
000
0
0
Bit 2
(continued)
Enable Arbitration Acceleration. When set to one, the PHY will
use the enhancements specified in Section 4.4 of 1394a-2000
specification. PHY behavior is unspecified if the value of
Enab_accel is changed while a bus request is pending.
Enable Multispeed Packet Concatenation. When set to one, the
link will signal the speed of all packets to the PHY.
Selects which of eight possible PHY register pages are accessible
through the window at PHY register addresses 1000
1111
If the page selected by Page_select presents per-port information,
this field selects which port’s registers are accessible through the
window at PHY register addresses 1000
Ports are numbered monotonically starting at zero, p0.
BStat
2
Int_enable
XXXXX
, inclusive.
Bit 3
Contents
RESERVED
Child
Fault
Bit 4
Description
Connected
XXXXX XXXXX XXXXX
Bit 5
2
through 1111
Data Sheet, Rev. 3
Bit 6
Bias
Agere Systems Inc.
2
through
2
May 2004
, inclusive.
Disabled
Bit 7