ISD5116SY Nuvoton Technology Corporation of America, ISD5116SY Datasheet - Page 33

• Manufacturer Part Number: ISD5116SY
• Description: IC VOICE REC/PLAY 8-16MN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5100r

Specifications of ISD5116SY

• Interface: I²C
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Microphone Inputs
The microphone inputs transfer the voice signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6
dB so a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across
the ANA OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p
into the storage array from a typical electric microphone output of 2 to 20 mV p-p. The input
impedance is typically 10kΩ.
The ACAP pin provides the capacitor connection for setting the parameters of the microphone AGC
circuit. It should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is
because the capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces
the amount of noise present in the output during quiet pauses. Tying this pin to ground gives
maximum gain; to VCCA gives minimum gain for the AGC amplifier but will cancel the AutoMute
function.
*DIFFERENTIAL PATH
6.4.6
6.4.7
AIG1
15
* FT HRU
* INP
* VOL
* FIL TO
* SUM1
* SUM2
AIG0
14
Ana Out Description
Analog Inputs
AIPD
13
AXG1 AXG0 AXPD
1 2
3 (AOS 2,AOS1,AOS 0)
11
1 0
AOS2
0
0
0
0
1
1
1
1
INS 0
9
AOS1
A OS2 AOS1
0
0
1
1
0
0
1
1
8
AOS0
7
0
1
0
1
0
1
0
1
- 33 -
AOS0 A OPD
6
SOURCE
FTHRU
FILTO
SUM1
SUM2
VOL
INP
N/C
N/C
5
(AOPD)
1
OPS1
4
(1 Vp -p m a x. from AU X IN o r AR R AY)
(69 4 mVp-p ma x. fro m mi crop ho ne inp ut)
OPS0 OPA1
3
Publication Release Date: Oct 31, 2008
A NA OUT+
A NA OUT–
2
AOPD
ISD5100 SERIES
0
1
OPA0 VL PD
1
CONDITION
Power Up
Power Down
0
Chip Set
CFG0
Revision 1.42