NS16C2752TVA/NOPB National Semiconductor, NS16C2752TVA/NOPB Datasheet - Page 2

• Manufacturer Part Number: NS16C2752TVA/NOPB
• Description: IC UART DUAL 64BYTE 44-PLCC
• Manufacturer: National Semiconductor

Specifications of NS16C2752TVA/NOPB

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NS16C2752TVA

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1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 System Block Diagram ..................................................................................................................... 4
4.0 Connection Diagrams ....................................................................................................................... 4
5.0 Pin Descriptions .............................................................................................................................. 5
6.0 Register Set .................................................................................................................................... 9
7.0 Operation and Configuration ........................................................................................................... 26
8.0 Design Notes ................................................................................................................................ 34
9.0 Absolute Maximum Ratings ............................................................................................................ 37
10.0 DC and AC Specifications ............................................................................................................. 37
11.0 Timing Diagrams ......................................................................................................................... 39
5.1 PARALLEL BUS INTERFACE .................................................................................................... 5
5.2 SERIAL IO INTERFACE ........................................................................................................... 6
5.3 CLOCK AND RESET ................................................................................................................ 8
5.4 POWER AND GROUND ........................................................................................................... 8
6.1 RECEIVE BUFFER REGISTER (RBR) ...................................................................................... 11
6.2 TRANSMIT HOLDING REGISTER (THR) .................................................................................. 12
6.3 INTERRUPT ENABLE REGISTER (IER) ................................................................................... 12
6.4 INTERRUPT IDENTIFICATION REGISTER (IIR) ........................................................................ 12
6.5 FIFO CONTROL REGISTER (FCR) .......................................................................................... 13
6.6 LINE CONTROL REGISTER (LCR) .......................................................................................... 16
6.7 MODEM CONTROL REGISTER (MCR) .................................................................................... 18
6.8 LINE STATUS REGISTER (LSR) ............................................................................................. 20
6.9 MODEM STATUS REGISTER (MSR) ....................................................................................... 22
6.10 SCRATCHPAD REGISTER (SCR) ......................................................................................... 23
6.11 PROGRAMMABLE BAUD GENERATOR ................................................................................ 23
6.12 ALTERNATE FUNCTION REGISTER (AFR) ............................................................................ 24
6.13 DEVICE IDENTIFICATION REGISTER (ID) ............................................................................. 24
6.14 ENHANCED FEATURE REGISTER (EFR) .............................................................................. 25
6.15 SOFTWARE FLOW CONTROL REGISTERS (SFR) ................................................................. 26
7.1 CLOCK INPUT ...................................................................................................................... 26
7.2 RESET ................................................................................................................................. 27
7.3 RECEIVER OPERATION ........................................................................................................ 27
7.4 TRANSMIT OPERATION ........................................................................................................ 29
7.5 SOFTWARE XON/XOFF FLOW CONTROL .............................................................................. 30
7.6 SPECIAL CHARACTER DETECT ............................................................................................ 31
7.7 SLEEP MODE ....................................................................................................................... 31
7.8 INTERNAL LOOPBACK MODE ............................................................................................... 31
7.9 DMA OPERATION ................................................................................................................. 31
7.10 INFRARED MODE ............................................................................................................... 32
8.1 DEBUGGING HINTS .............................................................................................................. 34
8.2 CLOCK FREQUENCY ACCURACY ......................................................................................... 34
8.3 CRYSTAL REQUIREMENTS ................................................................................................... 34
8.4 CONFIGURATION EXAMPLES ............................................................................................... 35
8.5 DIFFERENCES BETWEEN THE PC16552D AND NS16C2552/2752 ............................................ 35
8.6 NOTES ON TX FIFO OF NS16C2752 ....................................................................................... 36
10.1 DC SPECIFICATIONS .......................................................................................................... 37
10.2 CAPACITANCE ................................................................................................................... 37
10.3 AC SPECIFICATIONS .......................................................................................................... 37
7.3.1 Receive in FIFO Mode .................................................................................................. 27
7.3.2 Receive in non-FIFO Mode ............................................................................................ 28
7.3.3 Receive Hardware Flow Control ..................................................................................... 28
7.3.4 Receive Flow Control Interrupt ....................................................................................... 29
7.4.1 Transmit in FIFO Mode ................................................................................................. 29
7.4.2 Transmit in non-FIFO Mode ........................................................................................... 30
7.4.3 Transmit Hardware Flow Control .................................................................................... 30
7.4.4 Transmit Flow Control Interrupt ...................................................................................... 30
8.4.1 Set Baud Rate ............................................................................................................. 35
8.4.2 Configure Prescaler Output ............................................................................................ 35
8.4.3 Set Xon and Xoff flow control ......................................................................................... 35
8.4.4 Set Software Flow Control ............................................................................................. 35
8.4.5 Configure Tx/Rx FIFO Threshold .................................................................................... 35
8.4.6 Tx and Rx Hardware Flow Control .................................................................................. 35
8.4.7 Tx and Rx DMA Control ................................................................................................ 35
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