NS16C2752TVS/NOPB National Semiconductor, NS16C2752TVS/NOPB Datasheet - Page 22

• Manufacturer Part Number: NS16C2752TVS/NOPB
• Description: IC UART DUAL 64BYTE 48-TQFP
• Manufacturer: National Semiconductor

Specifications of NS16C2752TVS/NOPB

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NS16C2752TVS

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6.9 MODEM STATUS REGISTER (MSR)
This register provides the current state of the control lines
from the MODEM (or peripheral device) to the CPU. In addi-
tion to this current-state information, four bits of the MODEM
Bit
7
6
5
4
3
2
1
0
DDCD Input
DDSR Input
DCTS Input
DCD Input
DSR Input
CTS Input
Bit Name
Indicator
Indicator
Indicator
Edge RI
RI Input
Falling
Status
Status
Status
Status
Status
DCD
DSR
CTS
R/W
Def
RI
R
R
R
R
R
R
R
R
0
0
0
0
DCD Input Status
This bit is the complement of the Data Carrier Detect (DCD) input. In the loopback mode, this bit is
equivalent to the OUT2 of the MCR.
1 = DCD input is logic 0.
0 = DCD input is logic 1.
RI Input Status
This bit is the complement of the Ring Indicator (RI) input. In the loopback mode, this bit is equivalent
to OUT1 of the MCR.
1 = RI input is logic 0.
0 = RI input is logic 1.
DSR Input Status
This bit is the complement of the Data Set Ready (DSR) input. In the loopback mode, this bit is
equivalent to DTR in the MCR.
1 = DSR input is logic 0.
0 = DSR input is logic 1.
CTS Input Status
This bit is the complement of the Clear to Send (CTS) input. In the loopback mode, this bit is equivalent
to RTS in the MCR.
1 = CTS input is logic 0.
0 = CTS input is logic 1.
Delta DCD Input Indicator
This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD input has
changed state since the last read by the host.
1 = DCD input has changed state.
0 = DCD input has no state change (default).
Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status Interrupt is generated.
Falling Edge RI Indicator
This bit is theFalling Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the RI input pin has
changed from a logic 0 to 1 since the last read by the host.
1 = RI input has changed state from logic 0 to 1.
0 = RI input has no state change from 0 to 1 (default).
Delta DSR Input Indicator
This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the DSR input pin has
changed state since the last read by the host.
1 = DSR input has changed state from logic 0 to 1.
0 = DSR input has no state change from 0 to 1 (default).
Delta CTS Input Indicator
This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input pin has changed
state since the last time it was read by the host.
1 = CTS input has changed state.
0 = CTS input has no state change (default).
TABLE 13. MSR (0x6)
22
Status Register provide change information. The latter bits
are set to a logic 1 whenever a control input from the MODEM
changes state. They are reset to logic 0 whenever the CPU
reads the MODEM Status Register.
Description