550NE92M1600DGR Silicon Laboratories Inc, 550NE92M1600DGR Datasheet

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550NE92M1600DGR

Manufacturer Part Number
550NE92M1600DGR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of 550NE92M1600DGR

Lead Free Status / Rohs Status
Compliant
10 MH
V
Features
Applications
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXOs, where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory-configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating the long lead times associated with custom oscillators.
Functional Block Diagram
Rev. 0.6 6/07
O L TA G E
Available with any-rate output
frequencies from 10 to 945 MHz
and selected frequencies to
1.4 GHz
3rd generation DSPLL
superior jitter performance
3x better frequency stability than
SAW-based oscillators
SONET/SDH
xDSL
10 GbE LAN/WAN
Z T O
V
DD
Vc
Frequency
- C
Fixed
XO
O N T R O L L E D
ADC
1.4 G H
®
with
Clock Synthesis
10-1400 MHz
Any-rate
DSPLL
OE
Copyright © 2007 by Silicon Laboratories
®
Z
Low-jitter clock generation
Optical modules
Clock and data recovery
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Lead-free/RoHS-compliant
CLK–
C
GND
R Y S TA L
CLK+
®
circuitry to
O
S C I L L A T O R
GND
Ordering Information:
OE
V
C
Pin Assignments:
See page 8.
See page 7.
1
2
3
Si5602
(Top View)
R
Si550
(VCXO)
E V I S I O N
6
5
4
V
CLK–
CLK+
DD
Si550
D

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550NE92M1600DGR Summary of contents

Page 1

1 Features Available with any-rate output frequencies from 10 to 945 MHz and selected frequencies to ...

Page 2

Si 550 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current 2 Output Enable (OE) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further ...

Page 3

Table 3. CLK± Output Frequency Characteristics Parameter Symbol f 1,2,3 Nominal Frequency O 1,4 Temperature Stability 1,4 Absolute Pull Range APR Aging 5 Power up Time t OSC Notes: 1. See Section 3. "Ordering Information" on page 8 for further ...

Page 4

Si 550 Table 5. CLK± Output Phase Jitter Parameter Symbol 1,2,3 Phase Jitter (RMS) for F > 500 MHz OUT Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase ...

Page 5

Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,3 Phase Jitter (RMS) for F of 125 to 500 MHz OUT Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and ...

Page 6

Si 550 Table 7. CLK± Output Phase Noise (Typical) Offset Frequency 74.25 MHz 90 ppm/V LVPECL 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Table 8. Absolute Maximum Ratings Parameter Maximum Operating Temperature Supply ...

Page 7

Pin Descriptions Pin Name OE* 3 GND 4 CLK+ CLK– 5 (N/A for CMOS *Note: OE includes 17 kΩ pullup resistor to V ordering options. (Top View ...

Page 8

Si 550 3. Ordering Information The Si550 supports a variety of options including frequency, temperature stability, tuning slope, output format, and V . Specific device configurations are programmed into the Si550 at time of shipment. Configurations are DD specified using ...

Page 9

Si55x Mark Specification Figure 2 illustrates the mark specification for the Si550. Table 11 lists the line information. Table 11. Si55x Top Mark Description Line Position 1 1–10 “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number) ...

Page 10

Si 550 5. Outline Diagram and Suggested Pad Layout Figure 3 illustrates the package details for the Si550. Table 12 lists the values for the dimensions shown in the illustration. Table 12. Package Diagram Dimensions (mm) Dimension ...

Page 11

PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si550. Table 13 lists the values for the dimensions shown in the illustration. Table 13. PCB Land Pattern Dimensions (mm) Dimension ...

Page 12

Si 550 OCUMENT HANGE IST Revision 0.3 to Revision 0.4 Updated Table 1, “Recommended Operating Conditions,” on page 2. Added maximum supply current specifications. Specified relationship between temperature at startup and operation temperature. Added Output Enable active ...

Page 13

N : OTES Rev. 0.6 Si550 13 ...

Page 14

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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