552AF000105DG Silicon Laboratories Inc, 552AF000105DG Datasheet

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552AF000105DG

Manufacturer Part Number
552AF000105DG
Description
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of 552AF000105DG

Lead Free Status / Rohs Status
Compliant
D
O
Features
Applications
Description
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments typically found in communication
systems. The Si552 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
Rev. 0.6 6/07
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
jitter performance
3x better frequency stability than
SAW-based oscillators
SONET/SDH
xDSL
10 GbE LAN/WAN
U A L
S C I L L A T O R
®
circuitry to provide a very low jitter clock for all output frequencies.
F
R E Q U E N C Y
V
V
Frequency XO
DD
C
Fixed
ADC
®
with superior
( V C X O ) 1 0 MH
Clock Synthesis
10–1400 MHz
Any-rate
DSPLL
FS
Copyright © 2007 by Silicon Laboratories
®
V
O L TA G E
Low-jitter clock generation
Optical modules
Clock and data recovery
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
CLK-
GND
CLK+
- C
Z T O
O N T R O L L E D
1.4 G H
Ordering Information:
GND
Z
Pin Assignments:
FS
V
C
C
See page 8.
See page 7.
Si5602
(Top View)
1
2
3
R Y S TA L
R
Si 552
E V I S I O N
6
5
4
V
CLK–
CLK+
DD
Si552
D

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552AF000105DG Summary of contents

Page 1

Features Available with any-rate output frequencies from 10–945 ...

Page 2

Si 552 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current 2 Frequency Select (FS) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for ...

Page 3

Table 3. CLK± Output Frequency Characteristics Parameter Symbol 1,2,3 Nominal Frequency 1,4 Temperature Stability 1,4 Absolute Pull Range Aging 5 Power up Time Settling Time After FS Change Notes: 1. See Section 3. "Ordering Information" on page 8 for further ...

Page 4

Si 552 Table 5. CLK± Output Phase Jitter Parameter Symbol 1,2,3 Phase Jitter (RMS) for F > 500 MHz OUT Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase ...

Page 5

Table 5. CLK± Output Phase Jitter (Continued) Parameter Symbol 1,2,3 Phase Jitter (RMS) for F of 125 to 500 MHz OUT Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and ...

Page 6

Si 552 Table 7. CLK± Output Phase Noise (Typical) Offset Frequency 74.25 MHz 90 ppm/V LVPECL 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Table 8. Absolute Maximum Ratings Parameter Maximum Operating Temperature Supply ...

Page 7

Pin Descriptions Pin Name FS* 3 GND 4 CLK+ CLK– 5 (N/A for CMOS *Note: FS includes a 17 kΩ pullup resistor to V select and OE polarity ordering options. (Top View) ...

Page 8

Si 552 3. Ordering Information The Si552 supports a variety of options including frequency, temperature stability, tuning slope, output format, and V . Specific device configurations are programmed into the Si552 at time of shipment. Configurations are DD specified using ...

Page 9

Si55x Mark Specification Figure 2 illustrates the mark specification for the Si552. Table 11 lists the line information. Table 11. Si55x Top Mark Description Line Position 1 1–10 “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number) ...

Page 10

Si 552 5. Outline Diagram and Suggested Pad Layout Figure 3 illustrates the package details for the Si552. Table 12 lists the values for the dimensions shown in the illustration. Table 12. Package Diagram Dimensions (mm) Dimension ...

Page 11

PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si552. Table 13 lists the values for the dimensions shown in the illustration. Table 13. PCB Land Pattern Dimensions (mm) Dimension ...

Page 12

Si 552 OCUMENT HANGE IST Revision 0.3 to Revision 0.4 Updated Table 1, “Recommended Operating Conditions,” on page 2. Added maximum supply current specifications. Specified relationship between temperature at startup and operation temperature. Revision 0.4 to Revision ...

Page 13

N : OTES Rev. 0.6 Si552 13 ...

Page 14

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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