552CE000270DG Silicon Laboratories Inc, 552CE000270DG Datasheet - Page 5

• Manufacturer Part Number: 552CE000270DG
• Manufacturer: Silicon Laboratories Inc

Specifications of 552CE000270DG

• Lead Free Status / Rohs Status: Compliant

Table 5. CLK± Output Phase Jitter (Continued)
Table 6. CLK± Output Period Jitter
Phase Jitter (RMS)
for F
Notes:
Period Jitter*
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest K
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
OUT
requirements. See “AN266: VCXO Tuning Slope (K
rejection (PSR) advantage of Si55x versus SAW-based solutions.
of 125 to 500 MHz
Parameter
Parameter
1,2,3
Symbol
Symbol
J
PER
φ
J
Kv = 33 ppm/V
Kv = 45 ppm/V
Kv = 90 ppm/V
Kv = 135 ppm/V
Kv = 180 ppm/V
Kv = 356 ppm/V
50 kHz to 80 MHz (OC-192)
50 kHz to 80 MHz (OC-192)
50 kHz to 80 MHz (OC-192)
50 kHz to 80 MHz (OC-192)
50 kHz to 80 MHz (OC-192)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
12 kHz to 20 MHz (OC-48)
12 kHz to 20 MHz (OC-48)
12 kHz to 20 MHz (OC-48)
12 kHz to 20 MHz (OC-48)
12 kHz to 20 MHz (OC-48)
Test Condition
Test Condition
V
Rev. 0.6
Peak-to-Peak
), Stability, and Absolute Pull Range (APR)” for more information.
RMS
V
that meets the application’s minimum APR
Min
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.37
0.33
0.37
0.33
0.43
0.34
0.50
0.34
0.59
0.35
1.00
0.39
Typ
Typ
14
2
Max
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Si552
Units
Units
ps
ps
5