IS82C52Z Intersil, IS82C52Z Datasheet - Page 17

• Manufacturer Part Number: IS82C52Z
• Description: IC CONTROLLER UART 28-PLCC
• Manufacturer: Intersil

Specifications of IS82C52Z

• Features: Single Chip UART/BRG
• Number Of Channels: 1, UART
• Protocol: RS232C
• Voltage - Supply: 4.5 V ~ 5.5 V
• With Parallel Port: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 28-LCC (J-Lead)
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UART Timing Characterization
NOTES:
1. TBRE bit D6 in USR is updated each time TBRE changes state.
2. A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high.
3. A. With TR (Transmitter Register) initially empty, TDTX occurs from the 5th falling edge of CO(BRG) after WR goes high.
4. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.
5. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.
6. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.
B. With TR initially full, TCLTH(TBRE) occurs from the trailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by the
B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing edge
trailing edge of the 12th CO(BRG) in the last Stop bit.
of the 12th CO(BRG) in the last Stop bit.
CO(BRG)
INTR
SDI
RD
DR
NOTE 1
NOTE 2
TDRH
(25)
11
17
12
TIHF
(21)
(Continued)
13
LAST STOP BIT
FIGURE 19. RECEIVE TIMING
RBR
TRLDL
(26)
14
82C52
82C52
15
USR
16
TRLIL
(23)
START BIT / IDLE
1/I
2/I
3/I
April 26, 2006
FN2950.3