NOIL1SE3000A-GDC ON Semiconductor, NOIL1SE3000A-GDC Datasheet
NOIL1SE3000A-GDC
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NOIL1SE3000A-GDC Summary of contents
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... Bayer (RGB) patterned color filter array with micro lens. Contact your local ON Semiconductor representative for more information. ORDERING INFORMATION Marketing Part Number NOIL1SN3000A-GDC NOIL1SE3000A-GDC NOTE: Refer to Ordering Code Definition on page 54 for more information. © Semiconductor Components Industries, LLC, 2011 July, 2011 − Rev. 6 Figure 1. LUPA3000 Package Photo ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . ...
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... Operating ratings are conditions in which operation of the device is intended to be functional Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation. ...
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Electrical Specifications Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 5. POWER SUPPLY RATINGS Limits in bold apply for MIN MAX Symbol Power Supply V ...
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Table 7. AC ELECTRICAL CHARACTERISTICS The following specifications apply for VDD = 2.5 V Symbol Parameter F Input clock frequency CLK fps Frame rate 1. All parameters are characterized for DC conditions after thermal equilibrium is established. Combining Power Supplies ...
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The datasheet describes the interfaces of the LUPA3000. The CMOS image sensor features synchronous shutter with a maximum frame rate of 485 fps at full resolution. The sensor contains 64 on-chip 8-bit ADCs operating at 25.75 Msamples/s each, resulting in ...
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Figure 4. Micro Lens Behavior for Mono Figure 5. Micro Lens Behavior for Color http://onsemi.com 7 ...
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Image Sensor Core The LUPA3000 floor plan is shown in Figure 6. The sensor consists of the pixel array, column amplifiers, analog front end (AFE) consisting of programmable gain amplifier and ADCs, data block (not shown), sequencer, and LVDS transmitter ...
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Pixel Architecture The pixel architecture shown in Figure 8 features the global shutter combined with a high sensitivity and good parasitic light sensitivity (PLS). This pixel architecture is designed pixel pitch and ...
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Figure 10. Analog Frontend and ADC Concept Table 9. PROGRAMMABLE AMPLIFIERS GAIN SETTINGS Register Address d73 Bit 2 Bit The gain is set through bits ...
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The ADCs are designed using fully differential circuits to improve performance and noise immunity. In addition, a redundant signed digit (RSD) 1.5 bit per stage architecture with digital error correction is used to improve differential nonlinearity (DNL) and ensure that ...
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Table 11. AFE AND ADC PARAMETERS Parameter Total AFE + ADC latency Total AFE + ADC power (32 channels = 64 AFE + ADC) Protocol Layer Digital data from the ADCs is reorganized in the protocol layer before it is ...
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Data Block The data block is positioned in between the AFE (output stage + ADCs) and the LVDS interface. It multiplexes the outputs of two ADCs to one LVDS block and performs some minor data handling: • Calculate and insert ...
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... For example, if the master input clock runs at 206 MHz, 1/412 MHz = 2.41 ns adjustment resolution is possible. Refer to Sensor Clock Edge Adjust Register (b1000001 / d65) on page 26 for programming details. ON Semiconductor provides default settings for the programmable delay. These settings allow correct http://onsemi.com 14 Co mment s ...
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LVDS Specifications The LUPA3000 features a 33 channel LVDS data interface, which enables high data rates at a limited pin count with low power and noise. The LUPA3000 ...
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Table 12. LVDS DRIVER SPECIFICATIONS Parameter |V | (Note 1) Differential logic voltage T |V (1)|–|V (0)| Delta differential voltage Common mode offset OS d|V | Difference in common mode voltage for logic 1 and 0 OS ...
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On−Chip BandGap Reference and Current Biasing For current biasing and voltage reference requirements for the AFEs, ADCs, and LVDS I/O, LUPA3000 includes a bandgap voltage reference that is typically 1.25 V. This reference is used to generate the differential Vrefp–Vrefm ...
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Sequencer and Logic The sequencer generates the internal timing of the image core based on the SPI settings uploaded. You can control the following settings: • Window resolution • FOT and ROT • Enabling or disabling reduced ROT mode • ...
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Table 15. DETAILED DESCRIPTION OF SPI REGISTERS Address Bits 32 <7:0> SOF 33 <7:0> SOL 34 <7:0> EOL 35 <7:0> IDLE_A 36 <7:0> IDLE_B 64 <6:0> Voltage reference adjust <2:0> bg_trim <3> <6:4> vref_trim 65 <7:0> Clock edge delay <3:0> ...
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Table 15. DETAILED DESCRIPTION OF SPI REGISTERS Address Bits 101 <7:0> Testpattern 5 102 <7:0> Testpattern 6 103 <7:0> Testpattern 7 104 <7:0> Testpattern 8 105 <7:0> Testpattern 9 106 <7:0> Testpattern 10 107 <7:0> Testpattern 11 108 <7:0> Testpattern ...
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ROT. See ROT_timer (b0000001 / d1) on page 21. The default timing is in reduced ROT mode, so there is no reduction in dynamic range. • Ds_en, bit<3>. Bit to enable dual slope operation. Enabling this mode allows to ...
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Precharge_timer (b0000010 / d2) The precharge_timer register controls the length of the pixel precharge pulse as described in Frame Overhead Time on page 38. The pixel precharge length is expressed in the number of sensor clock periods by the following ...
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Y_end (b0001001 / d9 and b0001010 / d10) The Y_end register contains the row address of the last row to readout. Because a row address is 11-bit wide, the Y_end address is split over two registers: Y_end<10:8> and Y_end<7:0>. Y_end<10:8> ...
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Bias_col_load (b0001110 / d14) This register controls the biasing current of the column load. A higher biasing current has the following effects: • Faster settling on the pixel columns • Increased power consumption from Vpix. • Lower dark level Bias ...
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Fixed (b0011110 / d30) This register is read only and always returns 11000100. Table 32. FIXED REGISTER Value Effect On startup 11000100 Chip_rev_nb (b0011111 / d31) This register contains the revision number of the chip read only ...
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Sensor Clock Edge Adjust Register (b1000001 / d65) The sensor clock edge adjust programmable delay between the column readout and the ADC capture clock edges. The relationship is programmed to align to ±7 edges of the input high-speed clock (input ...
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These bits allow adjusting the rising edge of the sensor clock (CLK_SEN, clk/4) position, with respect to the high speed input clock (clk) and the falling edge of the ADC sample clock (ADC_CLK, clk/8). Table 40. DLY_SEN ...
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ADC and LVDS Channel Powerdown Registers (b1000010- 1000110 / d66-70) Each of the 32 data channels, sync, and clock out LVDS channels are individually powered down by setting the appropriate bits of these registers. Powering down a channel stops the ...
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LVDS Output Current Adjust Register (b1001000 / d72) The LVDS output drive current is adjusted with this control register. The startup value is b0110 that represents 3.76 mA, reflecting the typical LVDS operating point. There are 16 programmable values available. ...
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Testpattern 0-31 Registers (b1100000- 1111111 / d96-127) A register is provided for each of the 32 data channels for LVDS data recovery calibration, alignment, and testing. A unique test pattern is programmed for each data channel and Table 45. TEST ...
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Serial Peripheral Interface (SPI ) The SPI registers have an address space of 7 bits, a<6>–a<0>, and 8 data bits, d<7>–d<0>. A single instruction bit chooses between a read or write instruction. The SPI is used only after the clock ...
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This sensor supports multiple operation modes. The following list provides an overview. • Global shutter mode Pipelined global shutter mode ♦ Master mode • Slave mode • Triggered global shutter mode ♦ Master mode • Slave mode • Global Shutter ...
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External Trigger Integration Time Reset N Handling Readout FOT Handling É É É É É É É É É É É É É É É É É É É É ROT Line Readout Figure 20. Pipelined Shutter Operated in Slave ...
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Pixel Timing After every exposure cycle, the value on the pixel diode is transferred to the pixel storage capacitor. This is controlled by Vmem, precharge, and sample signals. The duration of this operation is the FOT. At the beginning of ...
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... Integration time) > Readout time In global shutter mode, the whole pixel array is integrated simultaneously. ON Semiconductor application note AN57864, Frame Rate Based on Integration Time. Figure 23. Timing Diagram Digital Signals LUPA3000 can operate in slave mode so, the pixel array of the image sensor requires different digital control signals ...
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Image Format and Readout Protocol The active area read out by the sequencer in full frame mode is shown in Figure 24. Pixels are always read in multiples of 32. 32 pixels Timeslot 1 Timeslot 53 Figure 24. Sensor Read ...
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When the EXPOSURE_1 signal goes low before the window readout has finished, the readout is interrupted after the completion of the current line’s readout (line x in Figure 27). FOT pix_vmem DATA EXPOSURE_1 pix_reset pix_sample Dual ...
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Data Stream Figure 29 represents the data stream of the data and control channels. Data channel “i” outputs the data from column “i” of every kernel. All control words in Table 49 can be uploaded through the SPI. A SOF ...
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Reduced ROT Readout Mode When a row is selected, each pixel sees a large capacitive load. This comes from two sections - 1) metal line connecting the pixel output to the column amplifier and parasitic caps of the 1695 pixels ...
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RESET_N RESET_N_SEQ LVDS output Sequencer Reset The sequencer is reset separately by bringing the RESET_N_SEQ register low. This causes an asynchronous reset of the sequencer. The reset must have a length of at least ...
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Windowing A fully configurable window can be selected for readout. The parameters to configure this window are: X_START the start position for the X readout. Readout starts only at odd kernel positions result possible start positions ...
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Figure 36. Dynamic Range Extended by Double Slope Capability In slave mode, you have full control through the pins Exposure 1 and Exposure 2. Configure the multiple slope parameters for the application and interpret the pixel data accordingly. Off-Chip FPN ...
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Software FPN Correction The procedure is as follows: 1. Adjust the black level with the help of histogram by modifying DAC offset. 2. Store a dark image by closing the lens aperture, but make sure no value is absolute zero. ...
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Pin Definitions The package has 369 pins. Table 51 lists 228 pins. The remaining pins are used as die attach ground pins. Table 51. PIN LIST Finger Number Pin Number ...
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Table 51. PIN LIST Finger Number Pin Number ...
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Table 51. PIN LIST Finger Number Pin Number ...
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Table 51. PIN LIST Finger Number Pin Number 124 V14 125 W14 126 W15 127 V15 128 U15 129 T15 130 T16 131 U16 132 V16 133 W16 134 W17 135 V17 136 U17 137 T17 138 T18 139 U18 ...
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Table 51. PIN LIST Finger Number Pin Number 166 E21 167 D21 168 D20 169 C20 170 C21 171 B21 172 A21 173 B20 174 A20 175 A19 176 B19 177 B18 178 A18 179 B17 180 A17 181 A16 ...
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... Die attach ground D/A Ground Die attach ground D/A Ground Die attach ground D/A Ground Die attach ground Non Assigned Pins Pins that are marked “not assigned” in the pin list must be left floating. ON Semiconductor uses some of them for debugging. http://onsemi.com 49 Description ...
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Figure 38. Visualization of Pin Assignment (Top View) http://onsemi.com 50 ...
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Mechanical Specifications Table 52. MECHANICAL SPECIFICATIONS Mechanical Specifications Die (Referenced to Die thickness Pin 1 being bottom left Die center, X offset to the center of package in Figure 39 on page 52) Die center, Y offset to the center ...
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Package Diagram INDEX MARK (PLATING OPTION) 4X (0.50X45°) CHAMFER Figure 39. LUPA3000 mPGA Package Diagram (Top View) GLASS PIN Fe-Ni-Co ALLOY http://onsemi.com 52 +0. 0.20) 0.15 369X ...
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CHAMFER Figure 40. LUPA3000 mPGA Package Diagram (Bottom View) http://onsemi.com 53 (AT PIN BASE) (AT PIN BASE) ALUMINA COAT 369X Ø0.97 ...
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... Figure 41 shows the transmission characteristics of the glass lid. Figure 41. Transmission Characteristics of Glass Lid For proper handling and storage conditions, refer to the ON Semiconductor application note AN52561, Image Sensor Handling and Best Practices. ON Semiconductor’s Image Sensor Business Unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to Seller’ ...
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Acronym Description ADC analog-to-digital converter AFE analog front end ANSI American National Standards Institute BGA ball grid array BL black pixel data CDM Charged Device Model CDS correlated double sampling CIS CMOS image sensor CMOS complementary metal oxide semiconductor CMY ...
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The leakage of charge from a saturated pixel into neighboring pixels. camera gain constant A constant that converts the number of electrons collected by a pixel into digital output (in DN). It can be extracted from photon transfer curves. ...
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Noise due to variation in the reset level of a pixel pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). ...
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