SI4322-A1-FTR Silicon Laboratories Inc, SI4322-A1-FTR Datasheet - Page 25

• Manufacturer Part Number: SI4322-A1-FTR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4322-A1-FTR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

5.14. FIFO Settings Command
Bit 7:4 <f3 : f0>:
Bit 3:2 <s1 : s0>:
Note: For details of the VDI (Valid Data Indicator) signal see the
The synchron pattern consists of two bytes. Byte 1 is fixed 2Dh, Byte 0 is programmable (default D4h) in the "5.6.
Synchron Pattern Command" on page 19.
Bit 1 <ff>:
Bit 0 <fe>:
Note: To restart the synchron word reception, the ff bit should be cleared and set. This action will initialize the FIFO and clear
The fe bit modifies the function of DATA (pin 6) and DCLK (pin 7) outputs. The DATA pin becomes FIFO select input (nFFS).
If the chip is used in FIFO mode, do not allow this to be a floating input. The DCLK pin changes to FIFO interrupt output
(FFIT) if this bit is set to 1.
Bit
its content.
15
1
14
1
Together with bits <f5 : f4> of the Extended Features Command (see below) determines the
FIFO IT level. The FIFO generates IT when the number of the received data bits reaches this
level.
Select the input of the FIFO fill start condition:
Enables FIFO fill after synchron word reception. FIFO fill stops when this bit is cleared.
Enables the 64-bit deep FIFO mode. To clear the counter of the FIFO, it has to be set to zero.
13
0
12
0
CR_LOCK
DQD
VDI
fifo fill enable <ff> *
fifo enable <fe> *
11
1
10
1
fifo enable*
s1
0
0
1
1
9
1
s0 FIFO Start Condition
0
1
0
1
8
0
Sync . W ord
EN
DIRECTION
Pad DATA
Detector
I/ O Port
nRES
Rev. 1.2
Synchron Pattern
f3
7
Q
Always
"5.5. Receiver Setting Command" on page 18
f2
SYNC. WORD
SYNC. WORD
6
VDI
logic HIGH
VDI
DATA (from data filter )
CLK (from clock recovery )
f1
NOTE:
* For details see the FIFO Settings Command
5
s0*
s1*
0
1
2
3
M
U
X
f0
4
FIFO W RITE Logic
s1
3
FIFO _WRITE_DATA
FIFO _WRITE_CLK
FIFO_WRITE_EN
nFIFO_RESET
(simplified)
s0
2
1
ff
fe
0
Si4322
CE87h
POR
.
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