LTC6360CMS8E#PBF Linear Technology, LTC6360CMS8E#PBF Datasheet - Page 13

• Manufacturer Part Number: LTC6360CMS8E#PBF
• Manufacturer: Linear Technology

Specifications of LTC6360CMS8E#PBF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

applicaTions inForMaTion
Input bias current induced DC voltage offsets can be
minimized by matching the parallel impedance of R
R
typical application when the amplifier is configured as a
unity gain buffer, choosing R
the offset. Since nonzero values of R
total output noise, R
to reduce the noise bandwidth.
Input Protection
Back-to-back diodes (D1 and D2 in Figure 5) are included
between +IN and –IN to protect the input devices. The
inputs do not have internal resistors in series with the
input transistors, a technique often used to protect the
input transistors from excessive current flow during an
overdrive condition. Adding series input resistors would
significantly degrade the low noise performance. Therefore,
if the voltage across the amplifier’s inputs is allowed to
exceed ±0.7V, steady state current conducted through the
protection diodes should be externally limited to ±10mA.
The input diodes are rugged enough to handle transient
currents due to amplifier slew rate overdrive or momentary
clipping without protection resistors.
Driving the input signal sufficiently beyond the specified
input common mode voltage range will cause the input
transistors to saturate. When saturation occurs, the ampli-
fier loses a stage of phase inversion and the output will
begin to invert. Diode D1 or D2 (Figure 5) forward biases
and holds the output within a diode drop of the input signal.
To avoid this inversion, limit the input drive to within the
specified input common mode range.
ESD
The LTC6360 has ESD protection diodes on all inputs
and outputs. The diodes are reverse biased during nor-
mal operation. If the input pins are driven beyond either
supply, large currents will flow through these diodes. If
the current is transient and limited to 10mA or less, no
damage to the device will occur.
G
to the source impedance, R
F
may be bypassed with a capacitor
F
equal to R
S
. For example, in the
F
will contribute to the
S
will minimize
F
and
On-Chip Charge Pump
A low noise on-chip charge pump generates a small nega-
tive voltage that is used to bias the output stage of the
amplifier, enabling output swing below 0V. The charge
pump output voltage is typically –0.6V. Several design
techniques have been used to lower the ripple present
at OUT due to the switching action of the charge pump.
The charge pump output is made available via the CPO
pin, and the amplifier’s charge pump input at the CPI pin.
This allows additional external filtering via a capacitor
connected from CPI to GND.
The charge pump operates at a nominal frequency of
10MHz. The output voltage at CPO will have small frequency
components at multiples of 5MHz. These components
are further reduced by the PSRR of the amplifier’s out-
put stage. The amplitude of the fundamental component
at the OUT pin is typically 1µV
capacitor at CPI.
Conventionally, a two chip solution is chosen to provide
output swing to true zero on a single supply: one ampli-
fier and an inverting charge pump to provide a negative
rail. Compared to a two chip solution, the LTC6360 offers
several advantages: a more compact layout with lower
part count, lower output ripple, less EMI and lower power.
Figure 6 shows the ripple voltage spectrum at the output,
V
OUT
, with a 0.1µF external CPI bypass capacitor.
0.1
10
1
0
INPUT GROUNDED
0.1µF CPI BYPASS CAPACITOR
Figure 6. Output Ripple Voltage
20
FREQUENCY (MHz)
40
RMS
60
with a 0.1µF bypass
LTC6360
80
6360 F06
100
13
6360f