SI3200-FSR Silicon Laboratories Inc, SI3200-FSR Datasheet - Page 74

• Manufacturer Part Number: SI3200-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3200-FSR

• Lead Free Status / Rohs Status: Compliant

Si3220/25 Si3200/02
The control byte has the following structure and is presented on the SDI pin MSB first:
See Table 42 for bit definitions.
74
3:0
7
6
5
4
REG/RAM Register/RAM Access Bit.
Reserved
BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is
CID[3:0]
R/W
BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3]
only valid for write operations since it would cause contention on the SDO pin during a
read.
Read/Write Bit.
0 = Write operation.
1 = Read operation.
0 = RAM access.
1 = Register access.
Indicates the channel that is targeted by the operation. Note that the 4-bit channel value is
provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to
the controller, and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 41.)
As the CID information propagates down the daisy chain, each channel decrements the
CID by 1. The SDI nodes between devices reflect a decrement of 2 per device since each
device contains two channels. The device receiving a value of 0 in the CID field responds
to the SPI transaction. (See Figure 42.) If a broadcast to all devices connected to the chain
is requested, the CID does not decrement. In this case, the same 8-bit or 16-bit data is pre-
sented to all channels regardless of the CID values.
7
6
Table 42. SPI Control Interface
5
Rev. 1.3
4
3
2
1
0