DS2151Q/T&R Maxim Integrated Products, DS2151Q/T&R Datasheet - Page 27

IC TXRX T1 1-CHIP 5V LP 44-PLCC

DS2151Q/T&R

Manufacturer Part Number
DS2151Q/T&R
Description
IC TXRX T1 1-CHIP 5V LP 44-PLCC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS2151Q/T&R

Function
Single-Chip Transceiver
Interface
T1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
65mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-LCC, 44-PLCC
Includes
Alarm Detector and Generator, CSU Loop Codes Generator and Detector, DSX-1 and CSU Line Build-Outs Generator
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS2151Q/T&RDS2151Q/T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
6 ERROR COUNT REGISTERS
There are a set of three counters in the DS2151Q that record bipolar violations, excessive 0s, errors in the
CRC6 codewords, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on one second boundaries as
determined by the one second timer in Status Register 2 (SR2.5). Hence, these registers contain
performance data from the previous second. The user can use the interrupt from the 1-second timer to
determine when to read these registers. The user has a full second to read the counters before the data is
lost. All three counters will saturate at their respective maximum counts and they will not rollover (note:
only the Line Code Violation Count Register has the potential to overflow).
6.1 Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least
significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive 0s. See
B8ZS mode is set for the receive side via CCR2.2, then B8ZS codewords are not counted. This counter is
always enabled; it is not disabled during receive loss of synchronization (RLOS = 1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)
Table 6-1. Line Code Violation Counting Arrangements
EXCESSIVE 0S?
LCV15
(MSB)
LCV7
(RCR1.7)
COUNT
SYMBOL
LCV15
Yes
Yes
LCV0
No
No
LCV14
LCV6
ENABLED?
(CCR2.2)
LCV13
LCV5
B8ZS
Yes
POSITION
Yes
LCVCR1.7
LCVCR2.0
No
No
LCV12
LCV4
BPVs + 16 consecutive 0s
Table 6-1
BPVs + 8 consecutive 0s
BPVs (B8ZS codewords
WHAT IS COUNTED
NAME AND DESCRIPTION
MSB of the 16-bit code violation count
LSB of the 16-bit code violation count
not counted)
LCVCRs
IN THE
27 of 60
BPVs
LCV11
LCV3
for details of exactly what the LCVCRs count. If the
LCV10
LCV2
LCV9
LCV1
(LSB)
LCV8
LCV0
LCVCR1
LCVCR2
DS2151Q

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