SI3215-FT Silicon Laboratories Inc, SI3215-FT Datasheet - Page 35

• Manufacturer Part Number: SI3215-FT
• Description: IC SLIC/CODEC 1CH 38TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3215-FT

• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 5.25 V
• Current - Supply: 88mA
• Power (watts): 700mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Audio Tone Generation, BORSCHT Functions, FSK Generation, Voice Loopback Test Modes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.4. Enhanced FSK Waveform Generation
Enhanced FSK generation capabilities can be enabled
by setting FSKEN = 1 (direct Register 108, bit 6) and
REN = 1 (direct Register 32, bit 6). In this mode, the
user can define mark (1) and space (0) attributes once
during initialization by defining indirect registers 69–74.
The user need only indicate 0-to-1 and 1-to-0 transitions
in the information stream. By writing to FSKDAT (direct
Register 52), this mode applies a 24 kHz sample rate to
tone generator 1 to give additional resolution to timers
and frequency generation. “AN32: Si321x Frequency
Shift
instructions on how to implement FSK in this mode.
Additionally, sample source code is available from
Silicon Laboratories upon request.
2.4.5. Tone Generator Interrupts
Both the active and inactive timers can generate their
own interrupt to signal “on/off” transitions to the
software. The timer interrupts for tone generator 1 can
be individually enabled by setting the O1AE and O1IE
bits (direct Register 21, bits 0 and 1, respectively).
Timer interrupts for tone generator 2 are O2AE and
O2IE (direct Register 21, bits 2 and 3, respectively). A
pending interrupt for each of the timers is determined by
reading the O1AP, O1IP, O2AP, and O2IP bits in the
Interrupt Status 1 register (direct Register 18, bits 0
through 3, respectively).
Gen. 1
Output
Signal
OSS1
Tone
O1E
Keying
(FSK)
0,1
...
Modulation”
...
, O AT1
Figure 19. Tone Generator Timing Diagram
0,1
gives
...
detailed
Rev. 0.92
...
, OIT1
2.5. Ringing Generation
The ProSLIC provides fully-programmable internal
balanced ringing with or without a dc offset to ring a
wide variety of terminal devices. All parameters
associated with ringing, including ringing frequency,
waveform, amplitude, dc offset, and ringing cadence,
are
trapezoidal ringing waveforms are supported, and the
trapezoidal crest factor is programmable. Ringing
signals of up to 88 V peak or more can be generated,
enabling the ProSLIC to drive a 5 REN (1380 Ω +
40 µF) ringer load across loop lengths of 2000 feet
(160 Ω ) or more.
2.5.1. Ringing Architecture
The ringing generator architecture is nearly identical to
that of the tone generator. The sinusoid ringing
waveform is generated using an internal two-pole
resonance
frequency and amplitude. However, since ringing
frequencies are very low compared to the audio band
signaling
generated at a 1 kHz rate instead of 8 kHz.
The ringing generator has two timers that function the
same as for the tone generator timers. They allow on/off
cadence settings up to 8 seconds on/ 8 seconds off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the ringing state.
Table 28 summarizes the list of registers used for
ringing generation.
Note: Tone generator 2 should not be enabled concurrently
software-programmable.
with the ringing generator due to resource sharing
within the hardware.
0,1
...
frequencies,
oscillator
...
, O AT1
circuit
the
0,1
...
ringing
Both
with
sinusoidal
Si3215
programmable
waveform
...
...
and
35
is