DS3174+ Maxim Integrated Products, DS3174+ Datasheet - Page 211
DS3174+
Manufacturer Part Number
DS3174+
Description
IC TXRX DS3/E3 QUAD 400-BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3171N.pdf
(234 pages)
Specifications of DS3174+
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
4
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
725mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
400-BGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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13.2 JTAG TAP Controller State Machine Description
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. See
Figure 13-2
responds to the logic level at JTMS on the rising edge of JTCLK.
Figure 13-2. JTAG TAP Controller State Machine
Test-Logic-Reset. When JTRST is changed from low to high, the TAP controller starts in the Test-Logic-Reset
state, and the Instruction Register is loaded with the IDCODE instruction. All system logic and I/O pads on the
device operate normally. This state can also be reached from any other state by holding JTMS high and clocking
JTCLK five times.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The Instruction Register
and Test Register remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-
IR-Scan state.
Capture-DR. Data may be parallel loaded into the Test Data register selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test Register
remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or
to the Exit1-DR state if JTMS is high.
for details on each of the states described below. The TAP controller is a finite state machine that
1
0
Test-Logic-Reset
Run-Test/Idle
0
1
1
0
Capture-DR
1
Select
DR-Scan
Shift-DR
Pause-DR
Update-DR
Exit1- DR
Exit2-DR
211
0
0
1
0
1
1
0
1
0
1
0
1
0
Capture-IR
1
Select
IR-Scan
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
0
0
1
0
1
1
0
1
0
1
0
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