DS21354LN+ Maxim Integrated Products, DS21354LN+ Datasheet - Page 74
DS21354LN+
Manufacturer Part Number
DS21354LN+
Description
IC TXRX E1 1-CHIP 3.3V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2154LNA2.pdf
(124 pages)
Specifications of DS21354LN+
Function
Single-Chip Transceiver
Interface
E1, HDLC
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
Remote and AIS Alarm Detector / Generator
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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HSR: HDLC STATUS REGISTER (Address = B1 Hex)
Note: The RPE, RPS, and TMEND bits are latched and are cleared when read.
SYMBOL
TMEND
(MSB)
RHALF
THALF
FRCL
FRCL
RNE
RPE
RPS
TNF
POSITION
RPE
HSR.7
HSR.6
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1)
consecutive zeros have been detected at RPOSI and RNEGI.
Receive Packet End. Set when the HDLC controller detects either the
finish of a valid message (i.e., CRC check complete) or when the
controller has experienced a message fault such as a CRC checking error,
or an overrun condition, or an abort has been seen. The setting of this bit
prompts the user to read the RHIR register for details.
Receive Packet Start. Set when the HDLC controller detects an opening
byte. The setting of this bit prompts the user to read the RHIR register for
details.
Receive FIFO Half Full. Set when the receive 64-byte FIFO fills beyond
the halfway point. The setting of this bit prompts the user to read the
RHIR register for details.
Receive FIFO Not Empty. Set when the receive 64-byte FIFO has at
least one byte available for a read. The setting of this bit prompts the user
to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64-byte FIFO
empties beyond the halfway point. The setting of this bit prompts the user
to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64-byte FIFO has at
least one byte available. The setting of this bit prompts the user to read the
THIR register for details.
Transmit Message End. Set when the transmit HDLC controller has
finished sending a message. The setting of this bit prompts the user to read
the THIR register for details.
RPS
RHALF
74 of 124
NAME AND DESCRIPTION
RNE
THALF
TNF
TMEND
(LSB)
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