DS21372T Maxim Integrated Products, DS21372T Datasheet - Page 6

• Manufacturer Part Number: DS21372T
• Description: IC TESTER BIT ERROR 3.3V 32-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21372T

• Function: Bit Error Rate Tester (BERT)
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Includes: Error Counter, Pattern Generator and Detector
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

2. PARALLEL CONTROL INTERFACE
The DS21372 is controlled via a multiplexed bi-directional address/data bus by an external
microcontroller or microprocessor. The DS21372 can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics for more details. The multiplexed bus on the DS21372 saves pins because the
address information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE (AS), at which time the DS21372
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during
the later portion of the DS or
latter portion of the DS or
impedance state as
DS21372 can also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update
counters and load transmit and receive pattern registers. At slow clock rates, sufficient time must be
allowed for these port operations.
3. PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
4. PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
(MSB)
PS31
PS23
PS15
PS7
PS30
PS22
PS14
PS6
RD
PS29
PS21
PS13
PS5
transitions high in Intel timing or as DS transitions low in Motorola timing. The
PS28
PS20
PS12
RD
WR
PS4
pulses. The read cycle is terminated and the bus returns to a high
pulses. In a read cycle, the DS21372 outputs a byte of data during the
PS27
PS19
PS11
PS3
PS26
PS18
PS10
PS2
6 of 22
PS25
PS17
PS9
PS1
(LSB)
PS24
PS16
PS8
PS0
PSR3 (addr.=00 Hex)
PSR2 (addr.=01 Hex)
PSR1 (addr.=02 Hex)
PSR0 (addr.=03 Hex)
DS21372