SI3220-KQ Silicon Laboratories Inc, SI3220-KQ Datasheet - Page 43

• Manufacturer Part Number: SI3220-KQ
• Description: IC SLIC/CODEC DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3220-KQ

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 65mA
• Power (watts): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Product: Telecom
• Supply Voltage (min): 3.13 V
• Supply Current: 22 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

So for a 90 V
crest factor of 1.3, the period is 0.05 s and the rise time
requirement is 0.015 s.
RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640)
RINGAMP = 90/160.8 x (2
RINGFREQ = (2 x RINGAMP)/(0.0153 x 8000) = 300
(0x012C)
The time registers and interrupts described in the
sinusoidal ring description also apply to the trapezoidal
ring waveform.
Ringing Coefficients
The ringing coefficients are calculated in decimal for
sinusoidal and trapezoidal waveforms. The RINGPHAS
and RINGAMP hex values are decimal to hex
conversions in 16-bit, 2’s complement representations
for their respective RAM locations.
To obtain sinusoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to a 24-bit 2’s
complement value. The lower 12 bits are placed in
RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are
cleared to 0. The upper 12 bits are set in a similar
manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the
sign bit and RINGFRHI bits 2:0 are cleared to 0.
For
RINGFREQ=0x7EFD9D are as follows:
RINGFRHI = 0x3F78
RINGFRLO = 0x6CE8
To obtain trapezoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to an 8-bit, 2’s
complement value. This value is loaded into RINGFRHI.
RINGFRLO is not used.
Figure 26. Trapezoidal Ringing Waveform
T
example,
=
V
Period
TIP-RING
V
PK
OFF
, 20 Hz trapezoidal waveform with a
=
------------- - CF
f
RING
the
1
t
RISE
15
T = 1/freq
) = 18340 (0x47A5)
=
register
desired crest factor
values
time
Preliminary Rev. 0.91
for
Ringing DC Offset Voltage
A dc offset voltage can be added to the Si3220’s ac
ringing waveform by programming the RINGOF RAM
location to the appropriate setting. The value of
RINGOF is calculated as follows:
External Unbalanced Ringing
The
unbalanced ringing schemes by providing a ringing
relay driver as well as inputs from an external ring trip
circuit. Using this scheme, line-card designers can use
the
architectures with minimal system changes.
Linefeed Overhead Voltage Considerations
During Ringing
The ringing mode output impedance allows ringing
operation
(VOVR = 0). If an offset of the ringing signal from the
ring lead is desired, VOVR can be used for this
purpose.
Ringing Power Considerations
The total power consumption of the Si3220/Si3200
chipset using internal ringing generation is dependent
on the VDD supply voltage, the desired ringing
amplitude, the total loop impedance, and the AC load
impedance (number of REN). The following equations
can be used to approximate the total current required
for each channel during ringing mode.
V
V
And
Where:
REN = number of REN
R
R
R
DD
DD
LOAD
LOOP
OUT
= 3.3 V:
= 5 V:
Dual
= ProSLIC output impedance = 320 Ω
Si3225
= 7000/REN for North America
I
= loop impedance
BAT,RMS
without
I
I
ProSLIC
DD,AVE
DD,AVE
supports
=
RINGOF
----------------------------------------------------------------
R
=
=
LOAD
overhead
22mA
26mA
Si3220/Si3225
chipset
v
+
=
RING,RMS
centralized,
R
-------------- -
64.32
+
+
V
LOOP
OFF
(
(
6mA REN
6mA REN
voltage
in
×
+
2
×
×
R
15
OUT
existing
battery-backed
)
)
×
modification
2.04
---------- -
π
system
43