DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet
DS21Q58L+
Specifications of DS21Q58L+
Related parts for DS21Q58L+
DS21Q58L+ Summary of contents
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GENERAL DESCRIPTION The DS21Q58 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines. The DS21Q58 is a direct replacement for the DS21Q50, with the addition of signaling access and improved interrupt handling ...
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ACRONYMS .......................................................................................................................6 2. DETAILED DESCRIPTION.................................................................................................6 3. BLOCK DIAGRAM .............................................................................................................7 4. PIN DESCRIPTION.............................................................................................................8 4 UNCTION ESCRIPTIONS 5. FUNCTIONAL DESCRIPTION .........................................................................................13 6. HOST INTERFACE PORT................................................................................................14 6 ARALLEL ORT PERATION 6 ERIAL ...
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LINE INTERFACE UNIT ...................................................................................................47 21 ECEIVE LOCK AND 21.1.1 Termination ...........................................................................................................................................47 21 ECEIVE ONITOR 21 RANSMIT AVESHAPING AND 21 ITTER TTENUATORS 21.4.1 Clock and Data Jitter Attenuators .........................................................................................................51 21.4.2 Undedicated ...
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Figure 3-1. Block Diagram ....................................................................................................................... 7 Figure 6-1. Serial Port Operation Mode 1 ...............................................................................................14 Figure 6-2. Serial Port Operation Mode 2 ...............................................................................................15 Figure 6-3. Serial Port Operation Mode 3 ...............................................................................................15 Figure 6-4. Serial Port Operation Mode 4 ...............................................................................................15 Figure 21-1 ...
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Table 4-1. Pin Description (Sorted by Function) ...................................................................................... 8 Table 4-2. Pin Assignments (Sorted by Number)....................................................................................10 Table 4-3. System (Backplane) Interface Pins ........................................................................................12 Table 4-4. Alternate Jitter Attenuator ......................................................................................................12 Table 4-5. Clock Synthesizer..................................................................................................................12 Table 4-6. Parallel Port Control Pins.......................................................................................................12 Table ...
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ACRONYMS The following abbreviations are used throughout this data sheet: FAS Frame Alignment Signal CAS Channel Associated Signaling MF Multiframe Si International Bits CRC4 Cyclical Redundancy Check CCS Common Channel Signaling Sa Additional bits E-Bit CRC4 Error Bits LOC ...
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BLOCK DIAGRAM Figure 3-1. Block Diagram MCLK VCO/PLL RECEIVE SIDE RRING1 RTIP1 TRANSMIT SIDE TRING1 TTIP1 Dallas Semiconductor DS21Q58 TRANSCEIVER PARALLEL AND TEST CONTROL PORT (ROUTED TO ALL BLOCKS) USER OUTPUT SELECT ELASTIC DATA STORE AND ...
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PIN DESCRIPTION Table 4-1. Pin Description (Sorted by Function) NAME PIN PARALLEL SERIAL PORT PORT ENABLED 71 4/8/16MCK AJACKI 69 AJACKO 50 ALE (AS)/A5 96 BTS0 97 BTS1 ...
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NAME PIN PARALLEL SERIAL PORT PORT ENABLED 89 RSYNC4 66 RTIP1 41 RTIP2 16 RTIP3 91 RTIP4 93 RVDD1 68 RVDD2 43 RVDD3 18 RVDD4 90 RVSS1 65 RVSS2 40 RVSS3 15 RVSS4 62 SYSCLK1 37 SYSCLK2 12 SYSCLK3 87 ...
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Table 4-2. Pin Assignments (Sorted by Number) NAME PIN PARALLEL SERIAL PORT PORT ENABLED 1 TTIP4 2 TVSS4 3 TVDD4 4 TRING4 5 TCLK4 6 TSER4 7 TSYNC4 8 DVSS4 9 DVDD4 10 OUTB3 11 OUTA3 12 SYSCLK3 13 RSER3 ...
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NAME PIN PARALLEL SERIAL PORT PORT ENABLED 55 TCLK2 56 TSER2 57 TSYNC2 58 DVSS2 59 DVDD2 60 OUTB1 61 OUTA1 62 SYSCLK1 63 RSER1 64 RSYNC1 65 RVSS2 66 RTIP1 67 RRING1 68 RVDD2 69 AJACKO 70 AJACKI 71 ...
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Pin Function Descriptions Table 4-3. System (Backplane) Interface Pins NAME TYPE Transmit Clock. TCLK is a 2.048MHz primary clock that is used to clock data through the transmit TCLK I formatter. Transmit Serial Data. Transmit NRZ serial data. TSER ...
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Table 4-7. Serial Port Control Pins NAME TYPE SDO O Serial Port Data Output. Data at this output can be updated on the rising or falling edge of SCLK. SDI I Serial Port Data Input. Data at this input can ...
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HOST INTERFACE PORT The DS21Q58 is controlled through either a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. See Table ...
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Figure 6-2. Serial Port Operation Mode 2 ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 0 (UPDATE SDO ON THE FALLING EDGE OF SCLK) SCLK SDI R/W ...
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REGISTER MAP Table 7-1. Register Map (Sorted by Address) ADDRESS TYPE CRCCR1 03 R CRCCR2 FASCR1 07 R FASCR2 08 R R/W 0B R/W ...
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ADDRESS TYPE 37 R/W 38 R/W 39 R/W 3A R/W 3B R/W 3C R/W 3D R/W 3E R/W 3F R/W Note 1: The device ID register and the system clock-interface control register exist in Transceiver 1 only (TS0, TS1 = ...
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Power-Up Sequence On power-up and after the supplies are stable, the DS21Q58 should be configured for operation by writing to all the internal registers (this includes setting the test register to 00h) since the contents of the internal registers ...
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Table 8-1. Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS present in frame N and FAS and FAS not present in frame Two valid MF alignment words found CRC4 within 8ms Valid MF ...
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CCR1 Register Name: Register Description: Common Control Register 1 Register Address: 12 Hex Bit # 7 6 Name FLB THDB3 NAME BIT Framer Loopback. See Section FLB loopback disabled 1 = loopback enabled Transmit HDB3 Enable THDB3 ...
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Framer Loopback When CCR1.7 is set to 1, the DS21Q58 enters a framer loopback (FLB) mode in testing and debugging applications. In FLB mode, the SCT loops data from the transmitter back to the receiver. When FLB is enabled, ...
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Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are ...
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Local Loopback When CCR4.6 is set to 1, the DS21Q58 is forced into local loopback (LLB) mode. In this loopback, data continues to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data ...
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CCR5 Register Name: Register Description: Common Control Register 5 Register Address: 16 Hex Bit # 7 6 Name LIUODO CDIG NAME BIT Line Interface Open-Drain Option. This control bit determines whether or not the TTIP and TRING outputs are open ...
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CCR6 Register Name: Register Description: Common Control Register 6 Register Address: 2F Hex Bit # 7 6 Name OTM1 OTM0 NAME BIT OTM1 7 Output Test Mode 1 Output Test Mode 0 OTM0 6 Signaling Read Access Select. This bit ...
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CCR7 Register Name: Register Description: Common Control Register 7 Register Address: 1F Hex Bit Name: — MM2 NAME BIT — 7 Unused. Should be set = 0 for proper operation. Monitor Mode 2. Sets the internal linear gain ...
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STATUS AND INFORMATION REGISTERS The DS21Q58 has a set of four registers that contain information about a framer’s real-time status. The registers include status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status register ...
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Interrupt Handling The host can quickly determine which status registers in the four ports are causing an interrupt by reading one of the unused addresses such as 0Ch, 0Dh, or 0Eh in any port. Bit # 7 6 Name ...
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SSR Register Name: Register Description: Synchronizer Status Register Register Address: 09 Hex Bit # 7 6 Name CSC5 CSC4 NAME BIT CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CSC5 7 CSC4 6 CRC4 Sync Counter Bit 4 ...
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SR1 Register Name: Register Description: Status Register 1 Register Address: 0A Hex Bit # 7 6 Name RSA1 RDMA NAME BIT Receive Signaling All Ones. Set when the contents of time slot 16 contains fewer than three zeros over 16 ...
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IMR1 Register Name: Register Description: Interrupt Mask Register 1 Register Address: 18 Hex Bit # 7 6 Name RSA1 RDMA NAME BIT Receive Signaling All Ones RSA1 interrupt masked 1 = interrupt enabled Receive Distant MF Alarm ...
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SR2 Register Name: Register Description: Status Register 2 Register Address: 0B Hex Bit # 7 6 Name RMF RAF NAME BIT Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is RMF 7 enabled or not) on receive multiframe ...
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IMR2 Register Name: Register Description: Interrupt Mask Register 2 Register Address: 19 Hex Bit # 7 6 Name RMF RAF NAME BIT Receive CAS Multiframe RMF interrupt masked 1 = interrupt enabled Receive Align Frame 0 = ...
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ERROR COUNT REGISTERS Each DS21Q58 transceiver contains a set of four counters that record bipolar (BPVs) or code violations (CVs), errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the ...
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E-Bit/PRBS Bit-Error Counter E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 ...
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SIGNALING OPERATION Registers SA1 and SA16 are used to access the transmit and receive signaling function. Normally, reading these registers accesses the receive signaling data and writing these registers sources signaling data for the transmitter. The user can read ...
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DS0 MONITORING FUNCTION Each DS21Q58 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to ...
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CCR4 (Repeated here from Section Register Name: Register Description: Common Control Register 4 Register Address: 15 Hex Bit # 7 6 Name LIRST RESA NAME BIT LIRST 7 Line Interface Reset RESA 6 Receive Elastic Store Align RESR 5 Receive ...
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PRBS GENERATION AND DETECTION The DS21Q58 can transmit and receive the 2 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except TS0 any single time slot. ...
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SYSTEM CLOCK INTERFACE A single system clock interface (SCI) is common to all four DS21Q58 transceivers. The SCI is designed to allow any one of the four receivers to act as the master reference clock for the system. When ...
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TRANSMIT CLOCK SOURCE Depending on the DS21Q58’s operating mode, the transmit clock can be derived from different sources basic configuration, where the IBO function is disabled, the transmit clock is normally sourced from the TCLK pin. In ...
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PER-CHANNEL LOOPBACK The DS21Q58 has per-channel loopback capability that can operate in one of two modes: remote per-channel loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are looped back. In remote per-channel ...
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ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION On the receiver, the RAF and RNAF registers always report the data received in the additional (Sa) and international (Si) bit locations. The RAF and RNAF registers are updated ...
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TAF Register Name: Register Description: Transmit Align Frame Register Register Address: 20 Hex Bit # 7 6 Name Si 0 Note: This register must be programmed with the 7-bit FAS word. The DS21Q58 does not automatically set these bits. NAME ...
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USER-CONFIGURABLE OUTPUTS There are two user-configurable output pins for each transceiver, OUTA and OUTB. These pins can be programmed to output various clocks, alarms for line monitoring, or logic 0 and 1 levels to control external circuitry. They can ...
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Table 20-1. OUTA and OUTB Function Select OA3 OA2 OA1 OA0 OB3 OB2 OB1 OB0 ...
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LINE INTERFACE UNIT The line interface unit contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register (LICR), described below, ...
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Receive Monitor Mode When connecting to a monitor port, a large resistive loss is incurred due to the voltage divider between the E1 line termination resistors (Rt) and the monitor port isolation resistors (Rm) as shown in of the ...
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Transmit Waveshaping and Line Driving The DS21Q58 uses a set of laser-trimmed delay lines and a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications (Figure ...
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Figure 21-3. External Analog Connections (Protected Interface) FUSE TRANSMIT LINE FUSE FUSE RECEIVE LINE FUSE NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE 0.1mF. NOTE TRANSIENT SUPPRESSOR. NOTE 4: D1 ...
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Figure 21-4. Transmit Waveform Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 21.4 Jitter Attenuators The DS21Q58 contains an on-board clock and data jitter attenuator for each transceiver and a ...
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Undedicated Clock Jitter Attenuator The undedicated jitter attenuator is useful for preparing a user-supplied clock for use as a transmission clock (TCLK). AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of ...
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CODE MARK INVERSION (CMI) The DS21Q58 provides a CMI interface for connecting to optical transports. This interface is a unipolar 1T2B- coded signal. Ones are alternately encoded as a logical level for the full duration of ...
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Transmit and receive CMI is enabled through OUTAC.7. When this register bit is set, the TTIP pin outputs CMI- coded data at normal TTL-type levels. This signal can be used to directly drive an optical interface. When CMI is enabled, ...
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INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher-speed PCM buses to simplify transport across the system backplane. The DS21Q58 can be configured to allow PCM data buses to be multiplexed ...
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Figure 23-1. IBO Configuration Using Two DS21Q58 Transceivers (Eight E1 Lines) XFMR TTIP1/TRING1 E1 #1 XFMR RTIP1/RRING1 XFMR TTIP2/TRING2 E1 #2 XFMR RTIP2/RRING2 XFMR TTIP3/TRING3 E1 #3 XFMR RTIP3/RRING3 XFMR TTIP4/TRING4 E1 #4 XFMR RTIP4/RRING4 XFMR TTIP1/TRING1 E1 #5 XFMR ...
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FUNCTIONAL TIMING DIAGRAMS 24.1 Receive Figure 24-1. Receive Frame and Multiframe Timing 1 FRAME RSYNC 2 RSYNC NOTE 1: RSYNC IN FRAME/OUTPUT MODE (RCR.6 = 0). NOTE 2: RSYNC IN MULTIFRAME/OUTPUT MODE (RCR.6 = 1). THIS ...
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Figure 24-4. Receive Interleave Bus Operation RSYNC 1 RSER FR1 CH32 2 RSER FR2 CH32 FR3 CH32 SYSCLK 3 RSYNC FRAMER 3, CHANNEL 32 RSER NOTE 1: 4.096MHZ BUS CONFIGURATION. NOTE 2: 8.192MHZ BUS CONFIGURATION. NOTE 3: RSYNC IS IN ...
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Transmit Figure 24-5. Transmit Frame and Multiframe Timing FRAME TSYNC 2 TSYNC NOTE 1: TSYNC IS IN FRAME MODE (TCR.1 = 0). NOTE 2: TSYNC IS IN MULTIFRAME MODE (TCR.1 = 1). Figure ...
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Figure 24-8. Framer Synchronization Flowchart esync 1 Increm ent ync C ounter FAS R ...
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Figure 24-9. Transmit Data Flow TAF TNAF.5-7 0 Pass-Through KEY: NOTE: AUTO REMOTE ALARM IF ENABLED WILL ONLY OVERWRITE BIT 3 OF TIME SLOT 0 IN THE NOT-ALIGN FRAMES IF THE ALARM NEEDS TO BE SENT. TSER 1 Time slot ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS21Q58L Operating Temperature Range for DS21Q58LN Storage Temperature Range Soldering Temperature Range Stresses beyond those listed under “Absolute Maximum Ratings” may cause ...
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AC TIMING PARAMETERS AND DIAGRAMS 26.1 Multiplexed Bus AC Characteristics Table 26-1. AC Characteristics—Multiplexed Parallel Port = 3.3V ±5 0°C to +70°C for DS21Q58L (Figure 26-1, Figure 26-2, and Figure PARAMETER Cycle Time ...
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Figure 26-1. Intel Bus Read AC Timing (PBTS = 0) ALE t ASD AD0–AD7 Figure 26-2. Intel Bus Write Timing (PBTS = 0) ALE t ASD AD0–AD7 t CYC PW ASH t ASED ...
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Figure 26-3. Motorola Bus AC Timing (PBTS = ASD R/W AD0–AD7 (READ) CS AD0–AD7 (WRITE) PW ASH t ASED t RWS t DDR t ASL t AHL ASL t AHL 65 ...
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Nonmultiplexed Bus AC Characteristics Table 26-2. AC Characteristics—Nonmultiplexed Parallel Port (V = 3.3V ±5 0°C to +70°C for DS21Q58L (Figure 26-4 through Figure 26-7) PARAMETER Setup Time for A0 to A7, Valid to CS ...
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Figure 26-5. Intel Bus Write Timing (PBTS = 0) A0–A7 D0– 0ns MIN WR Figure 26-6. Motorola Bus Read Timing (PBTS = 1) A0–A7 D0– 0ns MIN DS Figure 26-7. Motorola Bus Write Timing (PBTS ...
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Serial Port Table 26-3. AC Characteristics—Serial Port (BTS1 = 1, BTS0 = 0) = 3.3V ±5 0°C to +70°C for DS21Q58L 26-8) (Figure PARAMETER Setup Time CS to SCLK Setup Time SDI to ...
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Receive AC Characteristics Table 26-4. AC Characteristics—Receive (V = 3.3V ±5 0°C to +70°C for DS21Q58L (Figure 26-9 and Figure 26-10) PARAMETER SYSCLK Period SYSCLK Pulse Width RSYNC Setup to SYSCLK Falling RSYNC Pulse ...
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Figure 26-10. Receive AC Timing (Receive Elastic Store Enabled SYSCLK t D3 RSER 1 RSYNC 2 OUTA/OUTB 3 RSYNC NOTE 1: RSYNC IS IN OUTPUT MODE (RCR.5 = 0). NOTE 2: OUTA OR OUTB CONFIGURED AS CRCR MF ...
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Transmit AC Characteristics Table 26-5. AC Characteristics—Transmit (V = 3.3V ±5 0°C to +70°C for DS21Q58L (Figure 26-11 and Figure 26-12) PARAMETER TCLK Period TCLK Pulse Width TSYNC Setup to TCLK TSYNC Pulse Width ...
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Figure 26-12. Transmit AC Timing (IBO Enabled SYSCLK TSER NOTE: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF SYSCLK WHEN IBO MODE IS ENABLED. 26.6 Special Modes AC Characteristics Table 26-6. AC Characteristics—Special Modes (V = 3.3V ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo ...
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... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time DESCRIPTION © 2004 Maxim Integrated Products · Printed USA ...