DS26504L+ Maxim Integrated Products, DS26504L+ Datasheet - Page 5

• Manufacturer Part Number: DS26504L+
• Description: IC T1/E1/J1 64KCC ELEMENT 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS26504L+

• Function: BITS Element
• Interface: 64KCC, E1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Includes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

DS26504 T1/E1/J1/64KCC BITS Element
LIST OF FIGURES
Figure 3-1. Block Diagram ......................................................................................................................................... 11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ......................................................................................... 12
Figure 3-3. Transmit PLL Clock Mux Diagram .......................................................................................................... 12
Figure 3-4. Master Clock PLL Diagram ..................................................................................................................... 13
Figure 13-1. Basic Network Connection .................................................................................................................... 80
Figure 13-2. Typical Monitor Application ................................................................................................................... 82
Figure 13-3. CMI Coding ........................................................................................................................................... 84
Figure 13-4. Software-Selected Termination, Metallic Protection ............................................................................. 93
Figure 13-5. Software-Selected Termination, Longitudinal Protection ...................................................................... 94
Figure 13-6. E1 Transmit Pulse Template ................................................................................................................. 96
Figure 13-7. T1 Transmit Pulse Template ................................................................................................................. 96
Figure 13-8. Jitter Tolerance (T1 Mode).................................................................................................................... 97
Figure 13-9. Jitter Tolerance (E1 Mode).................................................................................................................... 97
Figure 13-10. Jitter Attenuation (T1 Mode)................................................................................................................ 98
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................................... 98
Figure 15-1. 64kHz Composite Clock Mode Signal Format .................................................................................... 100
Figure 17-1. JTAG Functional Block Diagram ......................................................................................................... 103
Figure 17-2. TAP Controller State Diagram............................................................................................................. 106
Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................................... 111
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................................... 111
Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................................... 111
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................................... 112
Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................................... 112
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................................... 112
Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................................... 113
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................................... 113
Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) ............................................................................... 117
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00) ................................................................................ 117
Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00)................................................................................... 118
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) ................................................................................ 120
Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01) ................................................................................ 120
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) ......................................................................... 121
Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01) ......................................................................... 121
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10.................................................................... 123
Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10.................................................................... 123
Figure 20-10. Receive Timing—T1, E1, 64KCC Mode............................................................................................ 125
Figure 20-11. Transmit Timing—T1, E1, 64KCC Mode........................................................................................... 127
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