DS21372T+ Maxim Integrated Products, DS21372T+ Datasheet - Page 12

• Manufacturer Part Number: DS21372T+
• Description: IC TESTER BIT ERROR 3.3V 32-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21372T+

• Function: Bit Error Rate Tester (BERT)
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Includes: Error Counter, Pattern Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

BIT COUNT REGISTERS
9. BIT ERROR COUNT REGISTERS
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,
the user must clear the BECR by either toggling the LC bit or pin. The DS21372 latches the bit error
count into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC
input pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by
an external processor to compute the BER performance on a loop or channel basis.
BIT ERROR COUNT REGISTERS
10. PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS21372. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS21372 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
(MSB)
BEC31 BEC30 BEC29 BEC28 BEC27 BEC26 BEC25 BEC24
BEC23 BEC22
BEC15 BEC14 BEC13 BEC12 BEC11 BEC10
(MSB)
BEC7
BC31
BC23
BC15
BC7
BEC6
BC30
BC22
BC14
BC6
BEC21 BEC20 BEC19 BEC18 BEC17
BEC5
BC29
BC21
BC13
BC5
BEC4
BC28
BC20
BC12
BC4
BEC3
BC27
BC19
BC11
BC3
BEC2
12 of 22
BC26
BC18
BC10
BC2
BEC9
BEC1
BC25
BC17
BC9
BC1
BEC16
(LSB)
BEC8
BEC0
(LSB)
BC24
BC16
BC8
BC0
BECR3 (addr.=0C Hex)
BECR2 (addr.=0D Hex)
BECR1 (addr.=0E Hex)
BECR0 (addr.=0F Hex)
BCR1 (addr.=0A Hex)
BCR0 (addr.=0B Hex)
BCR3 (addr.=08 Hex)
BCR2 (addr.=09 Hex)
DS21372