HI1-0303/883 Intersil, HI1-0303/883 Datasheet - Page 11
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HI1-0303/883
Manufacturer Part Number
HI1-0303/883
Description
Analog Switch Dual SPDT 14-Pin CDIP
Manufacturer
Intersil
Type
Analog Switchr
Datasheet
1.HI1-0303883.pdf
(11 pages)
Specifications of HI1-0303/883
Package
14CDIP
Maximum On Resistance
50@±15V Ohm
Number Of Channels Per Chip
2
Maximum Turn-off Time
250@±15V ns
Maximum Turn-on Time
300@±15V ns
Switch Architecture
SPDT
Power Supply Type
Single|Dual
SEATING
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
10. The maximum limits of lead dimensions b and c or M shall be
11. Dimensions b1 and c1 apply to lead base metal only. Dimension
12. Corner leads (1, N, N/2, and N/2+1) may be configured with a
13. This dimension allows for off-center lid, meniscus, and glass
14. Dimension Q shall be measured from the seating plane to the
15. Measure dimension S1 at all four corners.
16. N is the maximum number of terminal positions.
17. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
18. Controlling dimension: INCH.
PLANE
PLANE
9. Index area: A notch or a pin one identification mark shall be locat-
BASE
ccc
S1
b2
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
M applies to lead plating and finish thickness.
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
overrun.
base plane.
M
C A - B
b
bbb
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
S
S
C A - B
D
A
-A-
-B-
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
A
D
e
S
For information regarding Intersil Corporation and its products, see www.intersil.com
S
11
D
-C-
S
-D-
E
Q
aaa
A
L
M
M
c1
e
A/2
C A - B
SECTION A-A
LEAD FINISH
METAL
BASE
(b)
b1
α
S
M
e
A
c
D
S
HI-303/883
(c)
F14.3
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
eA/2
aaa
bbb
ccc
eA
S1
b1
b2
b3
c1
Q
M
A
D
E
α
N
b
c
e
L
MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
0.014
0.014
0.045
0.023
0.008
0.008
0.220
0.125
0.015
0.005
MIN
90
-
-
-
-
-
-
0.100 BSC
0.300 BSC
0.150 BSC
o
INCHES
14
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
0.200
0.060
0.015
0.030
0.010
0.0015
MAX
105
-
o
0.36
0.36
1.14
0.58
0.20
0.20
5.59
3.18
0.38
0.13
MIN
MILLIMETERS
90
-
-
-
-
-
-
o
2.54 BSC
7.62 BSC
3.81 BSC
14
19.94
5.08
0.66
0.58
1.65
1.14
0.46
0.38
7.87
5.08
1.52
0.38
0.76
0.25
0.038
MAX
105
-
o
Rev. 0 4/94
NOTES
2, 3
2
3
4
2
3
5
5
6
7
8
-
-
-
-
-
-
-
-
-
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