STM32F407IEH6 STMicroelectronics, STM32F407IEH6 Datasheet - Page 27
![Microcontrollers (MCU) ARM M4 512 FLASH 168 Mhz 192kB SRAM](/photos/40/79/407976/bga176_sml.jpg)
STM32F407IEH6
Manufacturer Part Number
STM32F407IEH6
Description
Microcontrollers (MCU) ARM M4 512 FLASH 168 Mhz 192kB SRAM
Manufacturer
STMicroelectronics
Datasheet
1.STM32F407ZGT6.pdf
(167 pages)
Specifications of STM32F407IEH6
Core
ARM Cortex M4
Processor Series
STM32F4
Data Bus Width
32 bit
Maximum Clock Frequency
168 MHz
Program Memory Size
512 KB
Data Ram Size
192 KB
On-chip Adc
Yes
Number Of Programmable I/os
140
Number Of Timers
10
Operating Supply Voltage
1.7 V to 3.6 V
Package / Case
UFBGA-176
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, I2C, I2S, SPI, UART
Program Memory Type
Flash
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F407IEH6
Manufacturer:
ST
Quantity:
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Company:
Part Number:
STM32F407IEH6
Manufacturer:
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Quantity:
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STM32F405xx, STM32F407xx
2.2.18
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when V
or when the device wakes up from the Standby mode (see
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the V
Low-power modes
The STM32F405xx and STM32F407xx support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
●
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
DD
power is not present. Backup registers are not reset by a system, a power reset,
DD
supply when present or from the V
Doc ID 022152 Rev 2
Section 2.2.18: Low-power
Section 2.2.18: Low-power
BAT
pin.
modes). It can be
Description
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