STM32F417ZGT6 STMicroelectronics, STM32F417ZGT6 Datasheet - Page 142

• Manufacturer Part Number: STM32F417ZGT6
• Description: Microcontrollers (MCU) ARM M4 1024 FLASH 168 Mhz 192kB SRAM
• Manufacturer: STMicroelectronics

Specifications of STM32F417ZGT6

• Core: ARM Cortex M4
• Processor Series: STM32F4
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 168 MHz
• Program Memory Size: 1024 KB
• Data Ram Size: 192 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 114
• Number Of Timers: 10
• Operating Supply Voltage: 1.7 V to 3.6 V
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 2
• Interface Type: CAN, I2C, I2S, SPI, UART
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Details

Electrical characteristics
Table 80.
1. C
2. Based on characterization, not tested in production.
142/168
t
d(NCE4_1-NIOWR)
t
t
t
h(NCEx-NIOWR)
d(NIORD-NCEx)
h(NCEx-NIORD)
t
t
t
t
su(D-NIORD)
h(NIOWR-D)
d(NIORD-D)
t
v(NIOWR-D)
t
L
Symbol
w(NIOWR)
w(NIORD)
= 30 pF.
Switching characteristics for PC Card/CF read and write cycles
NAND controller waveforms and timings
Figure 66
provide the corresponding timings. The results shown in this table are obtained with the
following FSMC configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
In all timing tables, the
in I/O space
FSMC_NIOWR low width
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
FSMC_NCE4_1 low to FSMC_NIOWR valid
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCEx low to FSMC_NIORD valid
FSMC_NCEx high to FSMC_NIORD) valid
FSMC_NIORD low width
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0.
through
(1)(2)
Figure 69
T
Parameter
HCLK
represent synchronous waveforms, and
is the HCLK clock period.
Doc ID 022063 Rev 2
5T
5T
8T
8T
8T
HCLK
HCLK
HCLK
HCLK
HCLK
Min
9
0
STM32F415xx, STM32F417xx
-
-
-
– 1.5
–1.5
–0.5
– 2
–1
Table 81
5T
5T
5T
HCLK
HCLK
HCLK
Max
-
-
-
-
-
-
-
+ 2.5
– 1
+ 2
and
Table 82
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns