AT32UC3C0512C-ALZT Atmel, AT32UC3C0512C-ALZT Datasheet - Page 29
AT32UC3C0512C-ALZT
Manufacturer Part Number
AT32UC3C0512C-ALZT
Description
512KB FLASH 144LQFP -40/125?C AUTO TRAY
Manufacturer
Atmel
Datasheet
1.AT32UC3C1512C-AZR.pdf
(106 pages)
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4.3.2.5
4.3.2.6
4.3.2.7
9166BS–AVR-02/11
Unaligned Reference Handling
Unimplemented Instructions
CPU and Architecture Revision
AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
Table 4-1.
The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
Three major revisions of the AVR32UC CPU currently exist. The device described in this
datasheet uses CPU revision 3.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled
for revision 1 or 2 is binary-compatible with revision 3 CPUs.
Instruction
ld.d
st.d
• All SIMD instructions
• All coprocessor instructions if no coprocessors are present
• retj, incjosp, popjc, pushjc
• tlbr, tlbs, tlbw
• cache
Instructions with Unaligned Reference Support
Supported Alignment
Word
Word
AT32UC3C
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