MICRF620 Micrel Inc, MICRF620 Datasheet - Page 14
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MICRF620
Manufacturer Part Number
MICRF620
Description
Manufacturer
Micrel Inc
Datasheet
1.MICRF620.pdf
(21 pages)
Specifications of MICRF620
Operating Temperature (min)
-20C
Operating Temperature Classification
Commercial
Modulation Type
FSK
Lead Free Status / Rohs Status
Not Compliant
Transceiver Sync/Non-Synchronous Mode
When Sync_en = 1, it will enable the bit synchronizer in
receive mode. The bit synchronizer clock needs to be
programmed,
synchronized clock will be set out on pit DataClk.
In transmit mode, when Sync_en = 1, the clock signal on
pin DataClk is a programmed bit rate clock. Now the
transceiver controls the actual data rate. The data to be
transmitted will be sampled on rising edge of DataClk. The
micro controller can therefore use the negative edge to
change the data to be transmitted. The clock used for this
purpose, BitRate-clock, is programmed in the same way
as the modulator clock and the bit synchronizer clock:
where
Data Interface
The MICRF620 interface can be divided in to two separate
interfaces, a “programming interface” and a “Data
interface”. The “programming interface” has a three wire
serial programmable interface and is described in chapter
Programming.
The “data interface” can be programmed to sync-/non-
synchronous mode. In synchronous mode the MICRF620
is defined as “Master” and provides a data clock that
allows users to utilize low cost micro controller reference
frequency.
Micrel, Inc.
July 2006
0000000
0000110
0000111 BitRate_clkS1 BitRate_clkS0
Sync_en
0
0
1
1
A6..A0
f
bit rate, should be equal to the bit rate (bit rate of 20
kbit/sec requires a clock frequency of 20kHz)
f
Refclk_K: 6 bit divider, values between 1 and 63
BitRate_clkS: Bit rate setting, values between 0 and
6
BITRATE_CLK
XCO
f
BITRATE_CL
: Crystal oscillator frequency
State
Rx: Bit
synchronization off
Tx: DataClk pin off
Rx: Bit
synchronization on
Tx: DataClk pin on
LNA_by
see
: The clock frequency used to control the
D7
-
K
=
chapter
Refclk_K
Comments
Transparent reception of data
Transparent transmission of
data
Bit-clock is generated by
transceiver
Bit-clock is generated by
transceiver
PA2
D6
‘0’
×
Bit
f
2
XCO
(7
-BITRATE_c
synchronizer.
RefClk_K5
PA1
D5
‘0’
lkS)
RefClk_K4
The
PA0
D4
‘0’
14
The data interface is defined in such a way that all user
actions should take place on falling edge and is illustrated
Figure 7 and 8. The two figures illustrate the relationship
between DATACLK and DATAIXO in receive mode and
transmit mode.
MICRF620 will present data on rising edge and the
“USER” sample data on falling edge in receive mode.
DATACLK
The User presents data on falling edge and MICRF620 samples
on rising edge in transmit mode.
Receiver
The receiver is a zero intermediate frequency (IF) type in
order to make channel filtering possible with low-power
integrated low-pass filters. The receiver consists of a low
noise amplifier (LNA) that drives a quadrature mixer pair.
The mixer outputs feed two identical signal channels in
phase quadrature. Each channel includes a pre-amplifier,
a third order Sallen-Key RC lowpass filter from strong
adjacent channel signals and finally a limiter. The main
channel filter is a switched-capacitor implementation of a
six-pole elliptic lowpass filter. The elliptic filter minimizes
the total capacitance required for a given selectivity and
dynamic range. The cut-off frequency of the Sallen-Key
RC filter can be programmed to four different frequencies:
100kHz, 150kHz, 230kHz and 340kHz. The demodulator
demodulates the I and Q channel outputs and produces a
digital data output. If detects the relative phase of the I and
Q channel signal. If the I channel signal lags the Q
channel, the FSK tone frequency lies above the LO
frequency (data ‘1’). If the I channel leads the Q channel,
the FSK tone lies below the LO frequency (data ‘0’). The
output of the receiver is available on the DataIXO pin. A
RSSI circuit (receive signal strength indicator) indicates
the received signal level.
DATAIXO
BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
RefClk_K3
Sync_en
D3
DATACLK
DATAIXO
Figure 8. Data interface in Transmit Mode
Figure 7. Data interface in Receive Mode
RefClk_K2
Mode1
D2
RefClk_K1
MICRF620/MICRF620Z
Mode0
D1
M9999-120205
RefClk_K0
D0
’1’