LX16EVK01/NOPB National Semiconductor, LX16EVK01/NOPB Datasheet
LX16EVK01/NOPB
Specifications of LX16EVK01/NOPB
Related parts for LX16EVK01/NOPB
LX16EVK01/NOPB Summary of contents
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... Mbits/sec — 18–bit (max 900 Mbits/sec ■ 10 MHz to 50 MHz input clock support Typical Application Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS92LX1621 / DS92LX1622 ■ Embedded clock with DC Balanced coding to support AC- coupled interconnects ■ ...
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Block Diagrams Ordering Information NSID Package Description DS92LX1621SQE 32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch DS92LX1621SQ 32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch DS92LX1621SQX 32–pin LLP, 5.0 X 5.0 X 0.8 mm, ...
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DS92LX1621 Pin Diagram Serializer - DS92LX1621 — Top View 3 30123019 www.national.com ...
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DS92LX1621 Serializer Pin Descriptions Pin Name Pin No. LVCMOS PARALLEL INTERFACE DIN[13:0] 32, 31, 30, 29, Inputs, LVCMOS w/ 27, 26, 24, 23, 22, 21, 20, 19, 18, 17 HSYNC 1 Inputs, LVCMOS w/ VSYNC 2 Inputs, LVCMOS w/ PCLK ...
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DS92LX1622 Pin Diagram Deserializer - DS92LX1622 — Top View 5 30123020 www.national.com ...
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DS92LX1622 Deserializer Pin Descriptions Pin Name Pin No. LVCMOS PARALLEL INTERFACE ROUT[13:0] 9, 10, 11, 12, 14, Outputs, LVCMOS 15, 17, 18, 19, 20, 21, 22, 23, 24 HSYNC 7 Output, LVCMOS VSYNC 6 Output, LVCMOS PCLK 5 Output, LVCMOS ...
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Pin Name Pin No. RIN+ 35 Input/Output, CML RIN- 36 Input/Output, CML POWER AND GROUND VDDSSCG 4 Digital Power VDDOR1/2/3 25, 16, 8 Digital Power VDDD 13 Digital Power VDDR 30 Analog Power VDDCML 34 Analog Power VDDPLL 38 Analog ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( V ) DD1V8 Supply Voltage (V ) DD3V3 LVCMOS Input Voltage (V ) −0.3V to +(V DD1V8 LVCMOS Input Voltage (V ) −0.3V to +(V DD3V3 LVCMOS Output Voltage (V ...
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Symbol Parameter I Output Short Circuit Current OS I TRI-STATE® Output Current PDB = 0V, OZ CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT Output Differential Voltage OD Output Differential Voltage ΔV OD Unbalance Output Differential Offset V OS Voltage ...
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Symbol Parameter Deserializer (Rx) Supply I Current (includes load DDR current) I Deserializer (Rx) VDDIO DDIOR Supply Current (includes load current) I Deserializer (Rx) Supply DDRZ Current Power-down I DDIORZ Recommended Serializer Timing for PCLK Over recommended operating supply and ...
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Symbol Parameter t Serializer Output Random JINR Jitter Peak-to-peak Serializer t JINT Output Jitter Serializer Jitter Transfer λ STXBW Function -3 dB Bandwidth Serializer Jitter Transfer δ STX Function Serializer Jitter Transfer δ Function Peaking STXf Frequency Deserializer Switching Characteristics ...
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Bi-Directional Control Bus Timing Specifications (SCL, SDA) - (Figure 4) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter RECOMMENDED INPUT TIMING REQUIREMENTSRECOMMENDED INPUT TIMING REQUIREMENTS f SCL Clock Frequency SCL f SCL Low Period LOW f ...
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Bi-Directional Control Bus DC Characteristics (SCL, SDA Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis HY I TRI-STATE® Output OZ Current I Input Current IN C Input Pin Capacitance IN ...
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AC Timing Diagrams and Test Circuits FIGURE 6. Serializer CML Output Load and Transition Times www.national.com FIGURE 5. “Worst Case” Test Pattern 14 30123052 30123046 30123047 ...
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FIGURE 7. Serializer VOD DC Diagram FIGURE 8. Differential VTH/VTL Definition Diagram FIGURE 9. Serializer Input Clock Transition Times 15 30123048 30123030 30123016 www.national.com 30123034 ...
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FIGURE 10. Serializer Setup/Hold Times FIGURE 11. Serializer Data Lock Time FIGURE 12. Serializer Delay FIGURE 13. Deserializer Data Lock Time 16 30123049 30123032 30123050 30123013 ...
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FIGURE 14. Deserializer LVCMOS Output Load and Transition Times FIGURE 15. Deserializer Delay FIGURE 16. Deserializer Output Setup/Hold Times FIGURE 17. Spread Spectrum Clock Output Profile 17 30123014 30123011 30123031 30123035 www.national.com ...
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FIGURE 18. Typical Serializer Jitter Transfer Function at 43 MHz FIGURE 19. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz www.national.com 30123062 30123059 18 ...
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TABLE 1. DS92LX1621 Control Registers Addr Name Bits Field (Hex) 7:1 DEVICE Device SER ID 7:3 RESERVED 2 STANDBY 1 Reset DIGITAL 1 RESET0 0 DIGITAL RESET1 2 Reserved 7:0 RESERVED CRC Fault ...
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Addr Name Bits Field (Hex Bus Rate 7:0 7:1 DES DEV ID 6 DES ID 0 RESERVED 7:1 SLAVE DEV ID 7 Slave ID 0 RESERVED 8 Reserved 7:0 RESERVED 9 Reserved 7:0 RESERVED ...
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Addr Name Bits Field (Hex) 7:4 RESERVED 3:2 RESERVED 12 GPIO[5] Config 1 GPIO5 DIR 0 GPIO5 EN GPCR[7] GPCR[6] GPCR[5] GPCR[4] General Purpose 13 7:0 Control Reg GPCR[3] GPCR[2] GPCR[1] GPCR[0] R/W Default Description 0 Reserved 0 Reserved 0: ...
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TABLE 2. DS92LX1622 Control Registers Addr Name Bits (Hex) 7:1 DEVICE Device DES ID 7:3 RESERVED 2 REM_WAKEUP 1 Reset 1 DIGITALRESET0 0 DIGITALRESET1 Reserved 7:6 Auto Clock 5 AUTO_CLOCK OSS Select 4 ...
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Addr Name Bits (Hex) Tx CRC CHECK 7 ENABLE CRC Fault Tolerant Transmission Rx CRC GEN 6 ENABLE VDDIO VDDIO Control 5 CONTROL 3 VDDIO Mode 4 VDDIO MODE PASS Pass-Through 3 THROUGH Auto ...
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Addr Name Bits (Hex) Reserved 7 RESERVED SCL Prescale 6:4 SCL_PRESCALE REM_NACK_TIM 6 Remote NACK 3 ER Remote NACK 2:0 NACK_TIMEOUT 7:1 SER DEV ID 7 SER ID 0 RESERVED ID[0] Index 7:1 ID[0] INDEX 8 0 RESERVED 7:1 ID[1] ...
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Addr Name Bits (Hex) 7:1 ID[5] MATCH 15 ID[5] Match 0 RESERVED 7:1 ID[6] MATCH 16 ID[6] Match 0 RESERVED 7:1 ID[7] MATCH 17 ID[7] Match 0 RESERVED 18 Reserved 7:0 RESERVED 19 Reserved 7:0 RESERVED 1A CRC Errors 7:0 ...
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Addr Name Bits (Hex) 7:3 RESERVED 2 GPIO4 SET 21 GPIO[4] Config 1 GPIO4 DIR 0 GPIO4 EN 7:3 RESERVED 2 GPIO5 SET 22 GPIO[5] Config 1 GPIO5 DIR 0 GPIO5 EN GPCR[7] GPCR[6] GPCR[5] General Purpose GPCR[4] 23 7:00 ...
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Functional Description The DS92LX1621 / DS92LX1622 Channel Link III chipset is intended for camera applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 50 MHz pixel clock fre- quency. The DS92LX1621 transforms a 16-bit wide parallel LVCMOS data ...
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SLAVE CLOCK STRETCHING In order to communicate and synchronize with remote de- vices on the bus through the bi-directional control channel, slave clock stretching must be supported by the I controller/MCU. The chipset utilizes bus clock stretching ...
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Resistor RID Ω (±0.1%) 0 7b' 101 1000 (h'58) GND 2.0k 7b' 101 1001 (h'59) 4.7k 7b' 101 1010 (h'5A) 8.2k 7b' 101 1011 (h'5B) 12.1k 7b' 101 1100 (h'5C) 39.0k 7b' 101 1110 (h'5E) Resistor RID Ω (±0.1%) 0 ...
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At the same time, the Deserializer will capture the re- sponse on the bus and return the response as a command on the bi-directional control channel. The Serializer parses the response and passes the appropriate response ...
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FIGURE 26. Multiple Device Addressing 31 30123033 www.national.com ...
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PASS THROUGH pass-through provides an alternative means to indepen- dently address slave devices. The mode enables or disables bidirectional control channel communication to the remote bus. This option ...
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GENERAL PURPOSE I/O (GPIO) The DS92LX1621 / DS92LX1622 has GPIO (2 dedi- cated and 4 programmable). GPIO[0] and GPIO[1] are always available and GPIO[2:5] are available depending on the par- allel data bus size. DIN/ROUT[0:3] can be ...
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Note: AT-SPEED BIST is only available in the Camera mode and not the Display mode. Step 1: Place the Deserializer in BIST Mode. Serializer and Deserializer power supply must be supplied. Enable the AT SPEED BIST mode on the Deserializer ...
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Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail. To end BIST, the system must pull BISTEN pin of the Dese- rializer LOW. The BIST duration is fully defined by the BIS- ...
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The SER expects remote wake-up by default at power on. • Configure the control channel driver of the DES remote wake up mode by setting DES register 0x26 to 0xC0. • Perform remote wake up on ...
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Applications Information AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. To use For high-speed Channel Link III transmissions, the smallest available package should be used for the AC coupling ca- pacitor. This will ...
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FIGURE 35. DS92LX1621 Typical Connection Diagram 38 30123055 ...
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Figure 36 shows a typical connection of the DS92LX1622 Deserializer. FIGURE 36. DS92LX1622 Typical Connection Diagram 39 30123056 www.national.com ...
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TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination pro- viding a clean signaling environment. The interconnect for Channel Link ...
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Physical Dimensions inches (millimeters) unless otherwise noted DS92LX1621 Serializer NS Package Number SQA32A DS92LX1622 Deserializer NS Package Number SQA40A 41 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...