B300D44A102XXG ON Semiconductor, B300D44A102XXG Datasheet - Page 13

• Manufacturer Part Number: B300D44A102XXG
• Description: IC PROCESSOR AUDIO 24BIT 44DFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 300r
• Type: Audio Processorr

Specifications of B300D44A102XXG

• Applications: Portable Equipment
• Mounting Type: Surface Mount
• Package / Case: 44-VFDFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: B300D44A102XXG; B300D44A102XXGOSTR

CFX DSP Core
DSP core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture. It is able to perform two MACs,
two memory operations and two pointer updates per cycle,
making it well−suited to computationally intensive
algorithms.
The CFX features:
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The CFX DSP is a user−programmable general−purpose
Dual−MAC 24−bit load−store DSP core
Four 56−bit accumulators
Four 24−bit input registers
Support for hardware loops nested up to 4 deep
Combined XY memory space (48−bits wide)
Dual address generator units
Wide range of addressing modes:
♦
Direct
A Accumulators
B Accumulators
X Multiplier
Y Multiplier
X ALU and
Shifter
DCU
Y ALU
Y0
Y1
X0
X1
Pre−adder
Internal Routing
CTRL
X Data
Y Data
Interrupts
ILSR
ILPC
Immediate
SR
Figure 3. CFX DSP Core Architecture
LR
PC
X Round/
Y Round/
Saturate
Saturate
Hardware Loop
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DMU
Stack
PCU
X Sign/Zero
Y Sign/Zero
CTRL
Extend
Extend
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CFX DSP Architecture
types and sizes, peripherals, interrupt controllers, and
interfaces. Figure 3 illustrates the basic architecture of the
CFX. The control lines shown exiting the PCU indicate that
control signals go from the PCU to essentially all other parts
of the CFX.
simultaneous control of multiple computation units. The
DSP can execute up to four computation operations in
parallel with two data transfers (including rounding and/or
saturation as well as complex address updates), while
simultaneously changing control flow.
The CFX architecture encompasses various memory
The CFX employs a parallel instruction set for
♦
♦
♦
CTRL
Internal Routing
Instruction Bus
Indirect with post−modification
Modulo addressing
Bit reverse
Y Bus
X Bus
P Bus
Direct Addr
X AGU
Y AGU
SP Offset
Address and Control registers
Data registers
Y Bus
YMEM
XMEM
PMEM
X Bus
P Bus