AD9634BCPZ-210 Analog Devices Inc, AD9634BCPZ-210 Datasheet - Page 27

• Manufacturer Part Number: AD9634BCPZ-210
• Description: 58T8925
• Manufacturer: Analog Devices Inc

Specifications of AD9634BCPZ-210

• Resolution (bits): 12bit
• Sampling Rate: 210MSPS
• Input Channel Type: Differential
• Data Interface: Serial, SPI
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Rohs Compliant: Yes

MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Transfer Register
0xFF
ADC Function Registers
0x08
0x09
0x0B
0x0D
Register
Name
SPI port
configuration
Chip ID
Chip grade
Transfer
Power modes
Global clock
Clock divide
Test mode
Bit 7
(MSB)
0
Open
Open
Open
Open
Open
Test mode
0 = contin-
uous/
repeat
pattern
1 = single
pattern
then zeros
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Bit 5
Soft reset
Open
Open
Open
Reset PN
long gen
Input clock divider phase adjust
8-bit chip ID[7:0], AD9634 = 0x87 (default)
Speed grade ID;
00 = 250 MSPS
01 = 210 MSPS
11 = 170 MSPS
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
001 = 1 input clock cycle
Bit 4
1
Open
Open
Open
Reset PN
short gen
000 = no delay
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Bit 3
1
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
0100 = alternating checkerboard
0111 = one/zero word toggle
0110 = PN short sequence
0101 = PN long sequence
1001 to 1110 = unused
1000 = user test mode
0001 = midscale short
1111 = ramp output
0000 = off (default)
0011 = negative FS
Output test mode
0010 = positive FS
Bit 1
LSB first
Open
Open
Open
Internal power-down mode
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
00 = normal operation
01 = full power-down
11 = reserved
10 = standby
Bit 0
(LSB)
0
Open
Transfer
Duty cycle
stabilizer
(default)
Default
Value
(Hex)
0x18
0x00
0x00
0x01
0x00
0x00
0x87
AD9634
Default
Notes/
Comments
Nibbles are
mirrored so
that LSB-
first mode
or MSB-first
mode is set
correctly,
regardless
of shift
mode.
Read only.
Speed
grade ID
used to
differentiate
devices;
read only.
Synchro-
nously
transfers
data from
the master
shift
register to
the slave.
Determines
various
generic
modes of
chip
operation.
Clock divide
values other
than 000
auto-
matically
cause the
duty cycle
stabilizer to
become
active.
When this
register is
set, the test
data is
placed on
the output
pins in
place of
normal
data.