DF2117RVLP20HV Renesas Electronics America, DF2117RVLP20HV Datasheet - Page 233

• Manufacturer Part Number: DF2117RVLP20HV
• Description: MCU 16BIT FLASH 3V 160K 144-LGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117RVLP20HV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.2.60 (2)
SHLR (SHift Logical Right)
Operation
Rd (right logical shift)
Assembly-Language Format
SHLR.B #2, Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the right. Bit
1 shifts into the carry flag. Bits 7 and 6 are cleared to 0.
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Notes
Register direct
Addressing
Mode
SHLR (B)
Mnemonic
0
SHLR.B
MSB
Rd
b7
0
Operands
#2, Rd
b6
0
.
. . . . . .
.
1st byte
1
.
.
1
Condition Code
H: Previous value remains unchanged.
N: Always cleared to 0.
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 1.
.
2nd byte
4
.
Instruction Format
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 217 of 322
—
I
b1
rd
UI H
—
Section 2 Instruction Descriptions
LSB
b0
—
3rd byte
—
U
C
N
0
4th byte
REJ09B0139-0400
Z
Shift Logical
V
0
States
No. of
C
1